View FDC37B727-NS_8422969.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fdc37b72x 128 pin enhanced super i/o controller with acpi support features ? 5 volt operation ? pc98/99 and acpi 1.0 compliant ? battery back-up for wake-events ? isa host interface ? isa plug-and-play compatible register set - 12 irq options - 15 serial irq options - 16 bit address qualification - four dma options - 12ma at bus drivers ? bios buffer ? 20 gpi/o pins ? 32 khz standby clock output ? soft power management ? acpi/pme support ? sci/smi support - watchdog timer - power button override event - either edge triggered interrupts ? intelligent auto power management - shadowed write-only registers - programmable wake-up event interface ? 8042 keyboard controller - 2k program rom - 256 bytes data ram - asynchronous access to two data registers and one st atus register - supports interrupt and polling access - 8 bit timer/counter - port 92 support - fast gate a20 and hardware keyboard reset ? 2.88mb super i/o floppy disk controller - relocatable to 480 different addresses - licensed cmos 765b floppy disk controller - advanced digital data separator - smsc's proprietary 82077aa compatible core - sophisticated power control circuitry (pcc) including multiple powerdown modes for reduced power consumption - supports two floppy drives directly - software write protect - fdc on parallel port - low power cmos design - supports vertical recording format - 16 byte data fifo - 100% ibm ? compatibility - detects all overrun and underrun conditions - 24ma drivers and schmitt trigger inputs ? enhanced fdc digital data separator - low cost implementation - no filter components required - 2 mbps, 1 mbps, 500 kbps, 300 kbps, 250 kbps data rates - programmable precompensation modes ? serial ports - relocatable to 480 different addresses downloaded from: http:///
2 - two high speed ns16c550a compatible uarts with send/receive 16 byte fifos - programmable baud rate generator - modem control circuitry including 230k and 460k baud - irda 1.0, hp-sir, ask-ir support - ring wake filter ? multi-mode ? parallel port with chiprotect ? - relocatable to 480 different addresses - standard mode - ibm pc/xt ? , pc/at ? , and ps/2 ? compatible bidirectional parallelport - enhanced mode - enhanced parallel port (epp) compatible epp 1.7 and epp 1.9 (ieee 1284 compliant) - high speed mode - microsoft and hewlett packard extended capabilities port (ecp) compatible (ieee 1284 compliant) - incorporates chiprotect ? circuitry for protection against damage due to printer power-on - 14 ma output drivers ? 128 pin qfp package downloaded from: http:///
3 table of contents features ........................................................................................................................................... 1 general description ................................................................................................................. 5 description of pin functions ............................................................................................... 7 buffer type descript ions............................................................................... 10 general purpose i/o pins .......................................................................................................11 reference documents ............................................................................................................12 functional description ..........................................................................................................14 super i/o registers ........................................................................................... 14 host processor interfac e ............................................................................ 14 floppy disk controller .........................................................................................................15 fdc internal registers ...........................................................................................................15 command set/descriptions ...................................................................................................38 instruction set ............................................................................................................................41 data transfer commands ............................................................................... 53 control commands ........................................................................................... 62 serial port (uart) .......................................................................................................................69 infrared interfac e ........................................................................................... 85 parallel port ............................................................................................................................... 86 ibm xt/at compatible, bi-directional and epp modes ............................ 88 extended capabilities parallel port .............................................................................94 operatio n ............................................................................................................ 102 parallel port floppy disk controller ......................................................................107 power management .................................................................................................................109 uart power manageme nt .............................................................................. 113 parallel port .................................................................................................... 113 internal pwrgood ........................................................................................... 113 32.768 k h z standby clock output ................................................................ 114 serial irq ............................................................................................................................... ........115 bios buffer ............................................................................................................................... ....120 general purpose i/o ................................................................................................................121 descript ion......................................................................................................... 121 run state gpio data register access...................................................... 122 gpio configura tion ......................................................................................... 122 watch dog timer .......................................................................................................................126 downloaded from: http:///
4 8042 keyboard controller description .....................................................................128 soft power management .....................................................................................................136 button override feature ............................................................................. 139 acpi/pme/smi features ............................................................................................................141 acpi feature s..................................................................................................... 141 pme support ....................................................................................................... 143 acpi, pme and smi registers ............................................................................... 143 e ither e dge t riggered i nterrupts .............................................................................. 155 configuration ............................................................................................................................157 system elements .................................................................................................... 10 configuration sequence ................................................................................ 10 configuration registers .................................................................................. 162 operational description .....................................................................................................199 maximum guaranteed ratings* .......................................................................... 199 dc electrical characteristics ........................................................................ 199 ac timing ............................................................................................................... 204 capacitive loadin g........................................................................................... 204 ecp parallel port timing .............................................................................. 229 downloaded from: http:///
5 general description the fdc37b72x incorporates a keyboard interface, smsc's true cmos 765b floppy disk controller, advanced digita l data separator, 16 byte data fifo, two 16c550 compatible uarts, one multi-mode parallel port which includes chiprotect circuitry plus epp and ecp support, on-chip 12 ma at bus drivers, and two floppy direct drive support, soft power management and smi support and intelligent power management including pme and sci/acpi s upport. the true cmos 765b core provides 100% compatibility with ibm pc/xt and pc/at architectures in addition to providing data overflow and underflow protection. the smsc advanced digital data separator incorporates smsc's patented data separator technology, allowing for ease of testing and use. both on-chip uarts are compatible with the ns16c550a. the parallel port is compatible with ibm pc/at architecture, as well as epp and ecp. the fdc37b72x incorporat es sophisticated power control circuitry (pcc) which includes support for keyboard, mouse, modem ring, power button support and other wake-up events. the pcc supports multiple low power down modes. the fdc37b72x provides features for compliance with the advanced configuration and power interface specification (acpi). these features include s upport of both legacy and acpi power management models through the selection of smi or sci. it implements a power button override event (4 second button hold to turn off the system) and either edge triggered interrupts. the fdc37b72x provides support for the isa plug-and-play standard (version 1.0a) and provides for the recommended functionality to support windows '95/98 and pc98/pc99. through internal configur ation registers, each of the fdc37b72x's logical device's i/o address, dma channel and irq channel may be programmed. there are 480 i/o address location options, 12 irq pin options or serial irq option, and four dma channel options for each logical device. the fdc37b72x floppy disk controller and data separator do not require any external filter components and are therefore easy to use, offer lower system cost and reduced board area. the fdc is software and register compatible with smsc's proprietary 82077aa core. downloaded from: http:///
6 figure 1 - fdc37b72x pin configuration fdc37m72x 128 pin qfp 6463 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 iochrdy tc vcc drq3 ndack3 drq2 ndack2 drq1 ndack1 drq0 ndack0 reset_drv sd7 sd6 sd5 sd4 vss sd3 sd2 sd1 sd0 aen niow nior ser_irq/irq15 pci_clk/irq14/gp50 103104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 ncts2 nrts2 ndsr2 txd2/irtx rxd2/irrx ndcd2 vcc nri2 ndcd1 nri1 ndtr1 ncts1 nrts1/sysop ndsr1 txd1 rxd1 nstrobe nalf nerror nack busy pe slct vss pd7 ndtr2 32 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 34 35 36 37 38 drvden0 drvden1/gp52/irq8/nsmi nmtr0 nds1/gp17 nds0 nmtr1/gp16 vss ndir nstep nwdata nwgate nhdsel nindex ntrk0 nwrtprt nrdata ndskchg clk32out npoweron button_in npme/sci/irq9 clocki sa9 sa0sa1 sa2 sa4 sa6 sa7 sa8 sa3sa5 sa10 sa11 sa12 sa13 sa14 sa15 pd0 nslctin ninit vcc nromoe/irq12/gp54/eeti nromcs/irq11/gp53/eeti rd7/irq10/gp67 rd6/irq8/gp66 rd5/irq7/gp65 rd4/irq6/gp64/p17 rd3/irq5/gp63/wdt rd2/irq4/gp62/nring rd1/irq3/gp61/led rd0/irq1/gp60/nsmi kclk kdat vtr xtal2 avss xtal1 gp15/irtx2 vbat gp14/irrx2 gp13/led gp12/wdt/p17/eeti gp11/nring/eeti gp10/nsmi a20m kbdrst vss mclk mdat pd6 pd5 pd4 pd3 pd2 pd1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 downloaded from: http:///
7 description of pin functions table 1 - description of pin functions pin no./qfp name total symbol buffer type processor/host interface (40) 44-47, 49-52 system data bus 8 sd[0:7] io12 23-38 16-bit system address bus 16 sa[0:15] i 43 address enable 1 aen i 64 i/o channel ready 1 iochrdy od12 53 isa reset drive 1 reset_drv is 40 serial irq/irq15 1 ser_irq io12 39 pci clock/irq14/gp50 1 pci_clk io12 55 dma request 0 1 drq0 o12 57 dma request 1 1 drq1 o12 59 dma request 2 1 drq2 o12 54 dma acknowledge 0 1 ndack0 i 56 dma acknowledge 1 1 ndack1 i 58 dma acknowledge 2 1 ndack2 i 61 dma request 3 1 drq3 o12 60 dma acknowledge 3 1 ndack3 i 63 terminal count 1 tc i 41 i/o read 1 nior i 42 i/o write 1 niow i clocks (4) 22 14.318mhz clock input 1 clocki iclk 66 32.768khz crystal input 1 xtal1 iclk 68 32.768khz crystal driver 1 xtal2 oclk2 18 32.768khz clock out 1 clk32out o8 power pins (10) 62, 93, 121 +5v supply voltage 3 vcc 7, 48, 74, 104 digital ground 4 vss 67 analog ground 1 avss 69 trickle supply voltage 1 vtr 65 battery voltage 1 vbat power management (3) 19 power on 1 npoweron od24 20 button in 1 button_in i 21 power management event/sci/irq9 1 npme o12 fdd interface (16) 16 read disk data 1 nrdata is 11 write gate 1 nwgate o24 10 write disk data 1 nwdata o24 downloaded from: http:///
8 pin no./qfp name total symbol buffer type 12 head select 1 nhdsel o24 8 step direction 1 ndir o24 9 step pulse 1 nstep o24 17 disk change 1 ndskchg is 5 drive select 0 1 nds0 o24 6 drive select 1/gp17 1 nds1 io24 3 motor on 0 1 nmtr0 o24 4 motor on 1/gp16 1 nmtr1 io24 15 write protected 1 nwrtprt is 14 track 0 1 ntrko is 13 index pulse i nput 1 nindex is 1 drive density select 0 1 drvden0 o24 2 drive density select 1/gp52/irq8/nsmi 1 drvden1 io24 general purpose i/o (6) 77 general purpose 10/nsmi 1 gp10 io12 78 general purpose 11/nring/eeti (note 4) 1 gp11 io4 79 general purpose 12/wdt/p17/p12/eeti (note 4) 1 gp12 io4 80 general purpose 13/le d driver 1 gp13 io24 81 general purpose 14/infrared rx 1 gp14 io4 82 general purpose 15/infrared tx (note 3) 1 gp15 io24 bios interface (10) 83 rom bus 0/irq1/gp60/nsmi 1 rd0 io12 84 rom bus 1/irq3/gp61/led 1 rd1 io24 85 rom bus 2/irq4/gp62/nring 1 rd2 io12 86 rom bus 3/irq5/gp63/wdt 1 rd3 io12 87 rom bus 4/irq6/gp64/p17/p12 1 rd4 io12 88 rom bus 5/irq7/gp65 1 rd5 io12 89 rom bus 6/irq8/gp66 1 rd6 io12 90 rom bus 7/irq10/gp67 1 rd7 io12 91 nromcs/irq11/gp53/eeti (note 4) 1 nromcs io12 92 nromoe/irq12/gp54/eeti (note 4) 1 nromoe io12 serial port 1 interface (8) 112 receive serial data 1 1 rxd1 i 113 transmit serial data 1 1 txd1 o4 115 request to send 1 1 nrts1/ sysop io4 116 clear to send 1 1 ncts1 i 117 data terminal ready 1 1 ndtr1 o4 114 data set ready 1 1 ndsr1 i 119 data carrier detect 1 1 ndcd1 i 118 ring indicator 1 1 nri1 i serial port 2 interface (8) 123 receive serial data 2/in frared rx 1 rxd2/irrx i downloaded from: http:///
9 pin no./qfp name total symbol buffer type 124 transmit serial data 2/infrared tx (note 3) 1 txd2/irtx o24 126 request to send 2 1 nrts2 o4 127 clear to send 2 1 ncts2 i 128 data terminal ready 1 ndtr2 o4 125 data set ready 2 1 ndsr2 i 122 data carrier detect 2 1 ndcd2 i 120 ring indicator 2 1 nri2 i parallel port interface (17) 96-103 parallel port data bus 8 pd[0:7] iop14 95 printer select 1 nslctin op14 94 initiate output 1 ninit op14 110 auto line feed 1 nalf op14 111 strobe signal 1 nstrobe op14 107 busy signal 1 busy i 108 acknowledge handshake 1 nack i 106 paper end 1 pe i 105 printer selected 1 slct i 109 error at printer 1 nerror i keyboard/mouse interface (6) 70 keyboard data 1 kdat iod16 71 keyboard clock 1 kclk iod16 72 mouse data 1 mdat iod16 73 mouse clock 1 mclk iod16 75 keyboard reset 1 kbdrst (note 2) o4 76 gate a20 1 a20m o4 note 1: the n as the first letter of a signal name indicates an active low signal. note 2: kbdrst is active low. note 3: this pin defaults to an output and low. when configured as irtx (or irtx2), this pin is low when the ir block is not transmitting. note 4: eeti is the either edge tr iggered interrupt input function. downloaded from: http:///
10 buffer type descriptions table 2 - buffer types symbol description i input, ttl compatible. is input with schmitt trigger. iclk clock input. oclk2 clock output, 2ma sink, 2ma source. io4 input/output, 4ma sink, 2ma source. iop4 input/output, 4ma sink, 2ma source. backdrive protected. o4 output, 4ma sink, 2ma source. o8 output, 8ma sink, 4ma source. io12 input/output, 12ma sink, 6ma source. o12 output, 12ma sink, 6ma source. op12 output, 12ma sink, 6ma source. backdrive protected. od12 output, open drain, 12 ma sink. iop14 input/output, 14ma sink, 14ma source. backdrive protected. od14 output, open drain, 14ma sink. op14 output, 14ma sink, 14ma source. backdrive protected. iod16 input/output, open drain, 16ma sink o24 output, 24ma sink, 12ma source. od24 output, open drain, 24ma sink. downloaded from: http:///
11 general purpose i/o pins table 3 - general purpose i/o pin functions pin no. qfp default function alternate function 1 alternate function 2 alternate function 3 buffer type 5 index reg. gpio 77 gpio nsmi - - iop4/(op12/ od12) gp1 gp10 78 gpio nring eeti 1 - iop4/i/i gp1 gp11 79 gpio wdt p17/p12 4 eeti 1 iop4/o4/io4/i gp1 gp12 80 gpio led - - iop4/o24 gp1 gp13 81 gpio irrx2 - - iop4/i gp1 gp14 82 gpio irtx2 - - iop4/o24 gp1 gp15 4 nmtr1 gpio - - (o24/od24)/ iop4 gp1 gp16 6 nds1 gpio - - (o24/od24)/ iop4 gp1 gp17 39 pci_clk irq14 gpio - clkin/(o12/ od12)/iop4 gp5 gp50 2 drvden1 gpio irq8 nsmi (o24/od24) /iop4/ (op12/od12)/ (op12/od12) gp5 gp52 91 nromcs 2 irq11 gpio eeti 1 io12/(o12/ od12)/iop4/i gp5 gp53 92 nromoe 2 irq12 gpio eeti 1 io12/(o12/ od12)/iop4/i gp5 gp54 83 rd0 2,3 irq1 gpio nsmi io12/(o12/ od12)/iop4/ (op12/od12) gp6 gp60 84 rd1 2,3 irq3 gpio led io12/(o12/ od12)/iop4/ o24 gp6 gp61 85 rd2 2,3 irq4 gpio nring io12/(o12/ od12)/iop4/i gp6 gp62 86 rd3 2,3 irq5 gpio wdt io12/(o12/ od12)/iop4/ o4 gp6 gp63 87 rd4 2,3 irq6 gpio p17/p12 4 io12/(o12/ od12)/iop4/ io4 gp6 gp64 88 rd5 2,3 irq7 gpio - io12/(o12/ od12)/iop4 gp6 gp65 89 rd6 2,3 irq8 gpio - io12/(op12/ od12)/iop4 gp6 gp66 90 rd7 2,3 irq10 gpio - io12/(o12/ od12)/iop4 gp6 gp67 note 1: either edge triggered interrupt inputs. note 2: at power-up, rd0-7, nromcs and nromoe f unction as the xd bus. to use rd0-7 for alternate functions, nromcs must stay high until those pins are fini shed being programmed. note 3: these pins cannot be programmed as open drain pins in their original function. downloaded from: http:///
12 note 4: the function of p17 or p12 is selected via the p17/p12 select bit in the ring filter select register in logical device 8 at 0x c6. default is p17. note 5: buffer types per function are separated by a fo rward slash /. multiple buffer types per function are separated by a forward slash / and enclos ed in parentheses; e.g., irq outputs can be open drain or push-pull and are shown as (o12/od12). reference documents ? ieee 1284 extended capabilities port protocol and isa standard, rev. 1.14, july 14, 1993. ? hardware description of the 8042, intel 8 bit embedded controller handbook. ? pci bus power management interface specific ation, rev. 1.0, draft, march 18, 1997. downloaded from: http:///
13 figure 2 - fdc37b72x block diagram ndsr1, ndcd1, nri1, ndtr1 txd1 ninit, nalf host cpu multi-mode parallel port/fdc mux 16c550 compatible serial port 1 16c550 compatible serial port 2 with infrared configuration registers power management interface control bus address bus data bus nior niow aen sa[0:15] sd[o:7] drq[0:3] ndack [0:3] irq[1,3-12,14] reset_drv nindex ntrk0 ndskchg nwrprt nwgate densel ndir nstep nhdsel nds0,1 nmtr0,1 rdata rclock wdata wclock nwdata nrdata txd2(irtx) rxd2(irrx) ndsr2, ndcd2, nri2, ndtr2 rxd1 pd0-7 busy, slct, pe, nerror , nack nstb, nslctin , tc smsc proprietary 82077 compatible vertical floppydisk controller core digital data separator with write precom- pensation iochrdy bios buffer nromoe * nromcs * rd[0:7]* general purpose i/o gp1[0:7]* irrx 8042 kclk kdata mclk mdata p20, p21 xtal1 vbat drvden0 drvden1 *multi-function i/o pin - optional p17/p12* gp5[0,2:4]* gp6[0:7]* soft power management pme/ acpi npoweron button_in nsmi* vcc npme/sci serial irq ser_irq pci_clk vss clock gen clocki (14.318) clk32out nsmi vtr ncts2, nrts2 irtx ncts1, nrts1 xtal2 downloaded from: http:///
14 functional description super i/o registers the address map, shown below in table 1, shows the addresses of the differ ent blocks of the super i/o immediately after power up. the base addresses of the fdc, serial and parallel ports can be moved via the configur ation registers. some addresses are used to access more than one register. host processor interface the host processor communicates with the fdc37b72x through a series of read/write registers. the port addresses for these registers are shown in table 1. register access is accomplished through programmed i/o or dma transfers. all registers are 8 bits wide. all host interface output buffers are capable of sinking a minimum of 12 ma. table 4 - super i/o block addresses address block name logical device notes base+(0-5) and +(7) floppy disk 0 base+(0-3) base+(0-7) base+(0-3), +(400-402) base+(0-7), +(400-402) parallel port spp epp ecp ecp+epp+spp 3 base+(0-7) serial port com 1 4 base+(0-7) serial port com 2 5 ir support 60, 64 kybd 7 base + (0-17h) acpi, pme, smi a base + (0-1) configuration note 1: refer to the configuration register descriptions for setting the base address downloaded from: http:///
15 floppy disk controller the floppy disk controller (fdc) provides the interface between a host microprocessor and the floppy disk drives. the fdc integrates the functions of the formatter/ controller, digital data separator, write precompens ation and data rate selection logic for an ibm xt/at compatible fdc. the true cmos 765b core guarantees 100% ibm pc xt/at compatibility in addition to providing data overflow and underflow protection. the fdc is compatible to the 82077aa using smsc's proprietary floppy disk controller core. fdc internal registers the floppy disk controller contains eight internal registers that facilitate the interfacing between the host microprocessor and the disk drive. table 5 shows the addresses required to access these registers. registers other than the ones shown are not supported. the rest of the description assumes that the primary addresses have been selected. table 5 - status, data and control registers (shown with base addresses of 3f0 and 370) primary address secondary address r/w register 3f0 3f1 3f2 3f3 3f4 3f4 3f5 3f6 3f7 3f7 370 371 372 373 374 374 375 376 377 377 r r r/w r/w r w r/w r w status register a (sra) status register b (srb) digital output register (dor) tape drive register (tsr) main status register (msr) data rate select register (dsr) data (fifo) reserved digital input register (dir) configuration contro l register (ccr) downloaded from: http:///
16 status register a (sra) address 3f0 read only this register is read-only and monitors the state of the fintr pin and several disk interface pins in ps/2 and model 30 modes. the sra can be accessed at any time when in ps/2 mode. in the pc/at mode the data bus pins d0 - d7 are held in a high impedance state for a read of address 3f0. ps/2 mode bit 0 direction active high status indicating the direction of head movement. a logic "1" indicates inward direction; a logic "0" indicates outward direction. bit 1 nwrite protect active low status of the write protect disk interface input. a logic "0" indicates that the disk is write protected. (see al so force write protect function) bit 2 nindex active low status of the index disk interface input. bit 3 head select active high status of the hdsel disk interface input. a logic "1" selects side 1 and a logic "0" selects side 0. bit 4 ntrack 0 active low status of the trk0 disk interface input. bit 5 step active high status of the step output disk interface output pin. bit 6 ndrv2 active low status of t he drv2 disk interface input pin, indicating that a second drive has been installed. note: this function is not supported in this chip. (always 1, indicating 1 drive) bit 7 interrupt pending active high bit indicating the state of the floppy disk interrupt output. 7 6 5 4 3 2 1 0 int pending ndrv2 step ntrk0 hdsel nindx nwp dir reset cond. 0 1 0 n/a 0 n/a n/a 0 downloaded from: http:///
17 ps/2 model 30 mode bit 0 ndirection active low status indicating the direction of head movement. a logic "0" indicates inward direction; a logic "1" indicates outward direction. bit 1 write protect active high status of the write protect disk interface input. a logic "1" indicates that the disk is write protected. (see al so force write protect function) bit 2 index active high status of the index disk interface input. bit 3 nhead select active low status of the hdsel disk interface input. a logic "0" selects side 1 and a logic "1" selects side 0. bit 4 track 0 active high status of the trk0 disk interface input. bit 5 step active high status of the latched step disk interface output pin. this bit is latched with the step output going active, and is cleared with a read from the dir register, or with a hardware or software reset. bit 6 dma request active high status of the drq output pin. bit 7 interrupt pending active high bit indicating the state of the floppy disk interrupt output. 7 6 5 4 3 2 1 0 int pending drq step f/f trk0 nhdsel indx wp ndir reset cond. 0 0 0 n/a 1 n/a n/a 1 downloaded from: http:///
18 status register b (srb) address 3f1 read only this register is read-only and monitors the state of several disk interface pins in ps/2 and model 30 modes. the srb can be accessed at any time when in ps/2 mode. in the pc/at mode the data bus pins d0 - d7 are held in a high impedance state for a read of address 3f1. ps/2 mode bit 0 motor enable 0 active high status of the mtr0 disk interface output pin. this bit is low after a hardware reset and unaffected by a software reset. bit 1 motor enable 1 active high status of the mtr1 disk interface output pin. this bit is low after a hardware reset and unaffected by a software reset. bit 2 write gate active high status of the wgate disk interface output. bit 3 read data toggle every inactive edge of t he rdata input causes this bit to change state. bit 4 write data toggle every inactive edge of the wdata input causes this bit to change state. bit 5 drive select 0 reflects the status of the drive select 0 bit of the dor (address 3f2 bit 0). this bit is cleared after a hardware reset and it is unaffected by a software reset. bit 6 reserved always read as a logic "1". bit 7 reserved always read as a logic "1". 7 6 5 4 3 2 1 0 1 1 drive sel0 wdata toggle rdata toggle wgate mot en1 mot en0 reset cond. 1 1 0 0 0 0 0 0 downloaded from: http:///
19 ps/2 model 30 mode bit 0 ndrive select 2 the ds2 disk interface is not supported. (always 1) bit 1 ndrive select 3 the ds3 disk interface is not supported. (always 1) bit 2 write gate active high status of the latched wgate output signal. this bit is latched by the active going edge of wgate and is cleared by the read of the dir register. bit 3 read data active high status of the latched rdata output signal. this bit is latched by the inactive going edge of rdata and is clear ed by the read of the dir register. bit 4 write data active high status of the latched wdata output signal. this bit is latched by the inactive going edge of wdata and is cleared by the read of the dir register. this bit is not gated with wgate. bit 5 ndrive select 0 active low status of t he ds0 disk interface output. bit 6 ndrive select 1 active low status of t he ds1 disk interface output. bit 7 ndrv2 active low status of the drv2 disk interface input, this is not supported. (always 1). 7 6 5 4 3 2 1 0 ndrv2 nds1 nds0 wdata f/f rdata f/f wgate f/f nds3 nds2 reset cond. n/a 1 1 0 0 0 1 1 downloaded from: http:///
20 digital output register (dor) address 3f2 read/write the dor controls the drive select and motor enables of the disk interf ace outputs. it also contains the enable for the dma logic and a software reset bit. the contents of the dor are unaffected by a software reset. the dor can be written to at any time. bit 0 and 1 drive select these two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. bit 2 nreset a logic "0" written to this bit resets the floppy disk controller. this reset will remain active until a logic "1" is written to this bit. this software reset does not affect the dsr and ccr registers, nor does it affect the other bits of the dor register. the minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. bit 3 dmaen pc/at and model 30 mode: writing this bit to logic "1" will enable the drq, ndack, tc and fintr outputs. this bit being a logic "0" will disable the ndack and tc inputs, and hold the drq and fintr outputs in a high impedance state. this bit is a logic "0" after a reset and in these modes. ps/2 mode: in this mode the drq, ndack, tc and fintr pins are always enabled. during a reset, the drq, ndack, tc, and fintr pins will remain enabled, but this bit will be cleared to a logic "0". bit 4 motor enable 0 this bit controls the mtr0 disk interface output. a logic "1" in this bit will cause the output pin to go active. bit 5 motor enable 1 this bit controls the mtr1 disk interface output. a logic "1" in this bit will cause the output pin to go active. bit 6 motor enable 2 the mtr2 disk interface output is not. (always 0) bit 7 motor enable 3 the mtr3 disk interface output is not. (always 0) table 6 - drive activation values 7 6 5 4 3 2 1 0 mot en3 mot en2 mot en1 mot en0 dmaen nrese t drive sel1 drive sel0 reset cond. 0 0 0 0 0 0 0 0 drive dor value 0 1 1ch 2dh downloaded from: http:///
21 tape drive register (tdr) address 3f3 read/write table 7 - tape select bits the tape drive register (tdr) is included for 82077 software compatibility and allows the user to assign tape support to a particular driv e during initialization. any future references to that drive automatically invokes tape support. the tdr tape select bits tdr.[1:0] determine the tape drive number. table 7 illustrates the tape select bit encoding. note that drive 0 is the boot device and cannot be assigned tape support. the remaining tape drive register bits tdr.[7:2] are tristated when read. the tdr is unaffected by a software reset. table 8 - internal 2 drive decode - normal digital output register drive select outputs (active low) motor on outputs (active low) bit 7 bit 6 bit 5 bit 4 bit1 bit 0 nds1 nds0 nmtr1 nmtr0 x x x 1 0 0 1 0 nbit 5 nbit 4 x x 1 x 0 1 0 1 nbit 5 nbit 4 x 1 x x 1 0 1 1 nbit 5 nbit 4 1 x x x 1 1 1 1 nbit 5 nbit 4 0 0 0 0 x x 1 1 nbit 5 nbit 4 table 9 - internal 2 drive decode - drives 0 and 1 swapped digital output register drive select outputs (active low) motor on outputs (active low) bit 7 bit 6 bit 5 bit 4 bit1 bit 0 nds1 nds0 nmtr1 nmtr0 x x x 1 0 0 0 1 nbit 4 nbit 5 x x 1 x 0 1 1 0 nbit 4 nbit 5 x 1 x x 1 0 1 1 nbit 4 nbit 5 1 x x x 1 1 1 1 nbit 4 nbit 5 0 0 0 0 x x 1 1 nbit 4 nbit 5 tape sel1 (tdr.1) tape sel0 (tdr.0) drive selected 0 0 1 1 0 1 0 1 none 1 2 3 downloaded from: http:///
22 normal floppy mode normal mode. register 3f3 contains onl y bits 0 and 1. when this regist er is read, bits 2 - 7 are a high impedance. db7 db6 db5 db4 db3 db2 db1 db0 reg 3f3 tri-state tri-state tr i-state tri-state tr i-state tri-state t ape sel1 tape sel0 enhanced floppy mode 2 (os2) register 3f3 for enhanced floppy mode 2 operation. db7 db6 db5 db4 db3 db2 db1 db0 reg 3f3 reserved reserved drive type id floppy boot drive tape sel1 tape sel0 table 10 - drive type id digital output register register 3f3 - drive type id bit 1 bit 0 bit 5 bit 4 0 0 l0-crf2 - b1 l0-crf2 - b0 0 1 l0-crf2 - b3 l0-crf2 - b2 1 0 l0-crf2 - b5 l0-crf2 - b4 1 1 l0-crf2 - b7 l0-crf2 - b6 note: l0-crf2-bx = logical device 0, conf iguration register f2, bit x. downloaded from: http:///
23 data rate select register (dsr) address 3f4 write only this register is write only. it is used to program the data rate, amount of write precompensation, power down status, and software reset. the data rate is programmed us ing the configuration control register (ccr) not the dsr, for pc/at and ps/2 model 30 and microchannel applications. other applications can set the data rate in the dsr. the data rate of the floppy controller is the most rec ent write of either the dsr or ccr. the dsr is unaffected by a software reset. a hardware reset will set the dsr to 02h, which corresponds to the default precompensation setting and 250 kbps. 7 6 5 4 3 2 1 0 s/w reset power down 0 pre- comp2 pre- comp1 pre- comp0 drate sel1 drate sel0 reset cond. 0 0 0 0 0 0 1 0 bit 0 and 1 data rate select these bits control the data rate of the floppy controller. see table 11 for the settings corresponding to the individual data rates. the data rate select bits are unaffected by a software reset, and are set to 250 kbps after a hardware reset. bit 2 through 4 precompensation select these three bits select the value of write precompensation that w ill be applied to the wdata output signal. table 10 shows the precompensation values fo r the combination of these bits settings. track 0 is the default starting track number to start precompensation. this starting track number can be changed by the configure command. bit 5 undefined should be written as a logic "0". bit 6 low power a logic "1" written to this bit will put the floppy controller into manual low power mode. the floppy controller clock and data mode after a software reset or access to the data register or main status register. bit 7 software reset this active high bit has the same function as the dor reset (dor bit 2) except that this bit is self clearing. note: the dsr is shadowed in the floppy data rate select shadow register, ld8:crc2[7:0]. separator circuits will be turned off. the controller will come out of manual low power. downloaded from: http:///
24 table 11 - precompensation delays precomp 432 precompensation delay (nsec) <2mbps 2mbps 111 001 010 011 100 101 110 000 0.00 41.67 83.34 125.00 166.67 208.33 250.00 default 0 20.8 41.7 62.5 83.3 104.2 125 default default: see table 11 table 12 - data rates drive rate data rate data rate densel drate(1) drt1 drt0 sel1 sel0 mfm fm 1 0 0 0 1 1 1meg --- 1 1 1 0 0 0 0 500 250 1 0 0 0 0 0 1 300 150 0 0 1 0 0 1 0 250 125 0 1 0 0 1 1 1 1meg --- 1 1 1 0 1 0 0 500 250 1 0 0 0 1 0 1 500 250 0 0 1 0 1 1 0 250 125 0 1 0 1 0 1 1 1meg --- 1 1 1 1 0 0 0 500 250 1 0 0 1 0 0 1 2meg --- 0 0 1 1 0 1 0 250 125 0 1 0 drive rate table (recommended) 00 = 360k, 1.2m, 720k, 1.44m and 2.88m vertical format 01 = 3-mode drive 10 = 2 meg tape note 1: the drate and densel values are mapped onto the drvden pins. downloaded from: http:///
25 table 13 - drvden mapping dt1 dt0 drvden1 (1) drvden0 (1) drive type 0 0 drate0 densel 4/2/1 mb 3.5" 2/1 mb 5.25" fdds 2/1.6/1 mb 3.5" (3-mode) 1 0 drate0 drate1 0 1 drate0 ndensel ps/2 1 1 drate1 drate0 table 14 - default precompensation delays data rate precompensation delays 2 mbps 1 mbps 500 kbps 300 kbps 250 kbps 20.8 ns 41.67 ns 125 ns 125 ns 125 ns downloaded from: http:///
26 main status register address 3f4 read only the main status register is a read-only register and indicates the status of the disk controller. the main status register c an be read at any time. the msr indicates when the disk controller is ready to receive data via the data register. it should be read before each byte transferring to or from the data register except in dma mode. no delay is required when reading the msr after a data transfer. bit 0 - 1 drv x busy these bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates. bit 4 command busy this bit is set to a 1 when a command is in progress. this bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. if there is no result phase (seek, recalibrate commands), this bit is returned to a 0 after the last command byte. bit 5 non-dma this mode is selected in the specify command and will be set to a 1 during the execution phase of a command. this is for polled data transfers and helps differentiate betw een the data transfer phase and the reading of result bytes. bit 6 dio indicates the direction of a data transfer once a rqm is set. a 1 indicates a read and a 0 indicates a write is required. bit 7 rqm indicates that the host c an transfer data if set to a 1. no access is permitted if set to a 0. data register (fifo) address 3f5 read/write all command parameter information, disk data and result status are tran sferred between the host processor and the floppy disk controller through the data register. data transfers are governed by the rqm and dio bits in the main status register. the data register defaults to fifo disabled mode after any form of reset. this maintains pc/at hardware compatibility. t he default values can be changed through the configure command (enable full fifo operation with threshold control). the advantage of the fifo is that it allows the system a larger dma latency without causing a disk error. table 14 gives several examples of the delays with a fifo. the data is based upon the following formula: threshold # x 1 data rate x 8 - 1.5 s = delay at the start of a command, the fifo action is always disabled and command parameters must be sent based upon the rqm and dio bit settings. as the command executi on phase is entered, the fifo is cleared of any data to ensure that invalid data is not transferred. 7 6 5 4 3 2 1 0 rqm dio non dma cmd busy reserved reserved drv1 busy drv0 busy downloaded from: http:///
27 an overrun or underrun will terminate the current command and the transfer of data. disk writes will complete the current sector by generating a 00 pattern and valid crc. reads require the host to remove the remaining data so that the result phase may be entered. table 15 - fifo service delay fifo threshold examples maximum delay to servicing at 2 mbps data rate 1 byte 2 bytes 8 bytes 15 bytes 1 x 4 s - 1.5 s = 2.5 s 2 x 4 s - 1.5 s = 6.5 s 8 x 4 s - 1.5 s = 30.5 s 15 x 4 s - 1.5 s = 58.5 s fifo threshold examples maximum delay to servicing at 1 mbps data rate 1 byte 2 bytes 8 bytes 15 bytes 1 x 8 s - 1.5 s = 6.5 s 2 x 8 s - 1.5 s = 14.5 s 8 x 8 s - 1.5 s = 62.5 s 15 x 8 s - 1.5 s = 118.5 s fifo threshold examples maximum delay to servicing at 500 kbps data rate 1 byte 2 bytes 8 bytes 15 bytes 1 x 16 s - 1.5 s = 14.5 s 2 x 16 s - 1.5 s = 30.5 s 8 x 16 s - 1.5 s = 126.5 s 15 x 16 s - 1.5 s = 238.5 s downloaded from: http:///
28 digital input register (dir) address 3f7 read only this register is read-only in all modes. pc-at mode 7 6 5 4 3 2 1 0 dsk chg reset cond. n/a n/a n/a n/a n/a n/a n/a n/a bit 0 - 6 undefined the data bus outputs d0 - 6 will remain in a high impedance state during a r ead of this register. bit 7 dskchg this bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the force disk change register (see co nfiguration register ld8:crc1[1:0]). ps/2 mode bit 0 nhigh dens this bit is low whenever the 500 kbps or 1 mbps data rates are selected, and high when 250 kbps and 300 kbps are selected. bits 1 - 2 data rate select these bits control the data rate of the floppy controller. see table 11 for the settings corresponding to the individual data rates. the data rate select bits are unaffected by a software reset, and are set to 250 kbps after a hardware reset. bits 3 - 6 undefined always read as a logic "1" bit 7 dskchg this bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the force disk change register (see co nfiguration register ld8:crc1[1:0]). 7 6 5 4 3 2 1 0 dsk chg 1 1 1 1 drate sel1 drate sel0 nhigh ndens reset cond. n/a n/a n/a n/a n/a n/a n/a 1 downloaded from: http:///
29 model 30 mode bits 0 - 1 data rate select these bits control the data rate of the floppy controller. see table 11 for the settings corresponding to the individual data rates. the data rate select bits are unaffected by a software reset, and are set to 250 kbps after a hardware reset. bit 2 noprec this bit reflects the value of noprec bit set in the ccr register. bit 3 dmaen this bit reflects the value of dmaen bit set in the dor register bit 3. bits 4 - 6 undefined always read as a logic "0" bit 7 dskchg this bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the force disk change register (see co nfiguration register ld8:crc1[1:0]). 7 6 5 4 3 2 1 0 dsk chg 0 0 0 dmaen noprec drate sel1 drate sel0 reset cond. n/a 0 0 0 0 0 1 0 downloaded from: http:///
30 configuration control register (ccr) address 3f7 write only pc/at and ps/2 modes bit 0 and 1 data rate select 0 and 1 these bits determine the data rate of the floppy controller. see table 11 for the appropriate values. bit 2 - 7 reserved should be set to a logical "0" ps/2 model 30 mode bit 0 and 1 data rate select 0 and 1 these bits determine the data rate of the floppy controller. see table 11 for the appropriate values. bit 2 no precompensation this bit can be set by software, but it has no functionality. it can be read by bit 2 of the dsr when in model 30 register mode. unaffected by software reset. bit 3 - 7 reserved should be set to a logical "0" table 12 shows the state of the densel pin. the densel pin is set high after a hardware reset and is unaffected by the dor and the dsr resets. status register encoding during the result phase of certain commands, the data register contains data bytes that give the status of the command just executed. 7 6 5 4 3 2 1 0 d r a t e sel1 drate sel0 reset cond. n/a n/a n/a n/a n/a n/a 1 0 7 6 5 4 3 2 1 0 noprec drate sel1 drate sel0 reset cond. n/a n/a n/a n/a n/a n/a 1 0 downloaded from: http:///
31 table 16 - status register 0 bit no. symbol name description 7,6 ic interrupt code 00 - normal te rmination of command. the specified command was properly exec uted and completed without error. 01 - abnormal termination of command. command execution was started, but was not successfully completed. 10 - invalid command. the requested command could not be executed. 11 - abnormal termination caused by polling. 5 se seek end the fdc completed a seek, relative seek or recalibrate command (used during a sense interrupt command). 4 ec equipment check the trk0 pin failed to become a "1" after: 1. 80 step pulses in the recalibrate command. 2. the relative seek command caused the fdc to step outward beyond track 0. 3 unused. this bit is always "0". 2 h head address the current head address. 1,0 ds1,0 drive select t he current selected drive. downloaded from: http:///
32 table 17 - status register 1 bit no. symbol name description 7 en end of cylinder the fdc tried to access a sector beyond the final sector of the track (255d). will be set if tc is not issued after read or write data command. 6 unused. this bit is always "0". 5 de data error the fdc detected a crc error in either the id field or the data field of a sector. 4 or overrun/ underrun becomes set if the fdc does not receive cpu or dma service within the required time interval, resulting in data overrun or underrun. 3 unused. this bit is always "0". 2 nd no data any one of the following: 1. read data, read deleted data command - the fdc did not find the specified sector. 2. read id command - the fdc cannot read the id field without an error. 3. read a track command - the fdc cannot find the proper sector sequence. 1 nw not writeable wp pin became a "1" while the fdc is executing a write data, write deleted data, or format a track command. 0 ma missing address mark any one of the following: 1. the fdc did not detect an id address mark at the specified track after encount ering the index pulse from the idx pin twice. 2. the fdc cannot detect a data address mark or a deleted data address mark on the specified track. downloaded from: http:///
33 table 18 - status register 2 bit no. symbol name description 7 unused. this bit is always "0". 6 cm control mark any one of the following: 1. read data command - the fdc encountered a deleted data address mark. 2. read deleted data command - the fdc encountered a data address mark. 5 dd data error in data field the fdc detected a crc error in the data field. 4 wc wrong cylinder the track address from the sector id field is different from the track address maintained inside the fdc. 3 unused. this bit is always "0". 2 unused. this bit is always "0". 1 bc bad cylinder the track address from the sector id field is different from the track address maintained inside the fdc and is equal to ff hex, which indicates a bad track with a hard error according to the ibm soft-sectored format. 0 md missing data address mark the fdc cannot detect a data address mark or a deleted data address mark. table 19 - status register 3 bit no. symbol name description 7 unused. this bit is always "0". 6 wp write protected indicates the status of the wp pin. 5 unused. this bit is always "1". 4 t0 track 0 indicates the status of the trk0 pin. 3 unused. this bit is always "1". 2 hd head address indicates the status of the hdsel pin. 1,0 ds1,0 drive select indicates t he status of the ds1, ds0 pins. downloaded from: http:///
34 reset there are three sources of system reset on the fdc: the reset pin of the fdc, a reset generated via a bit in the dor, and a reset generated via a bit in the dsr. at power on, a power on reset initializes the fdc. all resets take the fdc out of the power down state. all operations are terminated upon a reset, and the fdc enters an idle state. a reset while a disk write is in progress w ill corrupt the data and crc. on exiting the reset state, various internal registers are cleared, in cluding the configure command information, and the fdc waits for a new command. drive polling will start unless disabled by a new configure command. reset pin (hardware reset) the reset pin is a global reset and clears all registers except those pr ogrammed by the specify command. the dor reset bit is enabled and must be cleared by the host to exit the reset state. dor reset vs. dsr reset (software reset) these two resets are functionally the same. both will reset the fdc core, which affects drive status information and the fifo circuits. the dsr reset clears itself automatica lly while the dor reset requires the host to manually clear it. dor reset has precedence over the dsr reset. the dor reset is set automatically upon a pin reset. the user must manually clear this reset bit in the dor to exit the reset state. modes of operation the fdc has three modes of operation, pc/at mode, ps/2 mode and model 30 mode. these are determined by the st ate of the ident and mfm bits 3 and 2 respectively of ld8crf0. pc/at mode - (ident high, mfm a "don't care") the pc/at register set is enabled, the dma enable bit of the dor becomes valid (fintr and drq can be hi z), and tc and densel become active high signals. ps/2 mode - (ident low, mfm high) this mode supports t he ps/2 models 50/60/80 configuration and register set. the dma bit of the dor becomes a "don't care", (fintr and drq are always valid), tc and densel become active low. model 30 mode - (ident low, mfm low) this mode supports ps/2 model 30 configuration and register set. the dma enable bit of the dor becomes valid (fintr and drq can be hi z), tc is active high and densel is active low. dma transfers dma transfers are enabled with the specify command and are initiated by the fdc by activating the fdrq pin during a data transfer command. the fifo is enabled directly by asserting ndack and addresses need not be valid. note that if the dma controller (i.e. 8237a) is programmed to function in verify mode, a pseudo read is performed by the fdc based only on ndack. this mode is only available when the fdc has been configured into byte mode (fifo disabled) and is programmed to do a read. with the fifo enabled, the fdc can perform the above operation by using the new verify command; no dma operation is needed. two dma transfer modes are supported for the fdc: single transfer and burst transfer. in the case of the single trans fer, the dma req goes active at the start of the dma cycle, and the dma req is deasserted after the ndack. in the case of the burst transfer, the req is held active until the last transfer (independent of ndack). see timing diagrams for more information. burst mode is enabled via bit[1] of crf0 in logical device 0. setting bit[1]=0 enables burst mode; the default is bit[1 ]=1, for non-burst mode. controller phases downloaded from: http:///
35 for simplicity, command handling in the fdc can be divided into three phases: command, execution, and result. each phase is described in the following sections. command phase after a reset, the fdc enters the command phase and is ready to accept a command from the host. for each of the commands, a defined set of command code bytes and parameter bytes has to be written to the fdc before the command phase is complete. (please refer to table 20 for the command set descriptions). these bytes of data must be transferred in the order prescribed. before writing to the fdc, the host must examine the rqm and dio bits of the main status register. rqm and dio must be equal to "1" and "0" respectively before command bytes may be written. rqm is set false by the fdc after each write cycle until the received byte is processed. the fdc asserts rqm again to request each parameter byte of the command unless an illegal command condition is detect ed. after the last parameter byte is received, rqm remains "0" and the fdc automatically enters the next phase as defined by the co mmand definition. the fifo is disabled during the command phase to provide for the proper handling of the "invalid command" condition. execution phase all data transfers to or from the fdc occur during the execution phase, which can proceed in dma or non-dma mode as indi cated in the specify command. after a reset, the fifo is disabled. each data byte is transferred by an fint or fdrq depending on the dma mode. the configure command can enable the fifo and set the fifo threshold value. the following paragraphs detail the operation of the fifo flow control. in these descriptions, is defined as the number of bytes available to the fdc when service is requested from the host and ranges from 1 to 16. the parameter fifothr, which the user programs, is one less and ranges from 0 to 15. a low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. the host reads (writes) from (to) the fifo until empty (full), then the transfer request goes inactive. the host must be very responsive to the service request. this is the desired case for use with a "fast" system. a high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. non-dma mode - transfers from the fifo to the host the fint pin and rqm bits in the main status register are activated when the fifo contains (16-) bytes or the last bytes of a full sector have been placed in the fifo. the fint pin can be used for interrupt-driven systems, and rqm can be used for polled systems. the host must respond to the request by reading data from the fifo. this process is repeated until the last byte is transferred out of the fifo. the fdc will deactivate the fint pin and rqm bit when the fifo becomes empty. downloaded from: http:///
36 non-dma mode - transfers from the host to the fifo the fint pin and rqm bit in the main status register are activated upon entering the execution phase of data transfer commands. the host must respond to the request by writing data into the fifo. the fint pin and rqm bit remain true until the fifo becomes full. they are set true again when the fifo has bytes remaining in the fifo. the fint pin w ill also be deactivated if tc and ndack both go inactive. the fdc enters the result phase after the la st byte is taken by the fdc from the fifo (i.e. fifo empty condition). dma mode - transfers from the fifo to the host the fdc activates the ddrq pin when the fifo contains (16 - ) bytes, or the last byte of a full sector transfer has been placed in the fifo. the dma controller must respond to the request by reading data from the fifo. the fdc will deactivate the ddrq pin when the fifo becomes empty. fdrq goes inactive after ndack goes active for the last byte of a data transfer (or on the active edge of nior, on the last byte, if no edge is present on ndack). a data underrun may occur if fdrq is not removed in time to prevent an unwanted cycle. dma mode - transfers from the host to the fifo. the fdc activates the fdrq pin when entering the execution phase of the data transfer commands. the dma controller must respond by activating the ndack and niow pins and placing data in the fifo. fdrq remains active until the fifo becomes full. fdrq is again set true when the fifo has bytes remaining in the fifo. the fdc will also deactivate the fdrq pin when tc becomes true (qualified by ndack), indicating that no more data is required. fdrq goes inactive after ndack goes active for the last byte of a data transfer (or on the active edge of niow of the last byte, if no edge is present on ndack). a data overrun may occur if fdrq is not removed in time to prevent an unwanted cycle. data transfer termination the fdc supports terminal count explicitly through the tc pin and implicitly through the underrun/overrun and end-of-track (eot) functions. for full sector transfers, the eot parameter can define the last sector to be transferred in a single or multi-sector transfer. if the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the fdc will continue to complete the sector as if a hardware tc was received. the only difference between these implicit functions and tc is that they return "abnormal termination" result status. such status indications can be ignored if they were expected. note that when the host is sending data to the fifo of the fdc, the inte rnal sector count will be complete when the fdc reads the last byte from its side of the fifo. there may be a delay in the removal of the transfer request signal of up to the time taken for the fdc to read the last 16 bytes from the fifo. the host must tolerate this delay. downloaded from: http:///
37 result phase the generation of fint determines the beginning of the result phase. fo r each of the commands, a defined set of result bytes has to be read from the fdc before the result phase is complete. these bytes of data must be read out for another command to start. rqm and dio must both equal "1" before the result bytes may be read. after all the result bytes have been read, the rqm and dio bits switch to "1" and "0" respectively, and the cb bit is cleared, indicating that the fdc is ready to accept the next command. downloaded from: http:///
38 command set/descriptions commands can be written whenever the fdc is in the command phase. each command has a unique set of needed param eters and status results. the fdc checks to see that the first byte is a valid command and, if valid, proceeds with the command. if it is invalid, an interrupt is issued. the user sends a sense interrupt status command which returns an invalid command error. refer to table 20 for explanations of the various symbols used. table 21 lists the required parameters and the results associated with each command that the fdc is capable of performing. table 20 - description of command symbols symbol name description c cylinder address the currently selected address; 0 to 255. d data pattern the pattern to be written in each sector data field during formatting. d0, d1 drive select 0-1 designates whic h drives are perpendic ular drives on the perpendicular mode command. a "1" indicates a perpendicular drive. dir direction control if this bit is 0, then t he head will step out from the spindle during a relative seek. if set to a 1, the head will step in toward the spindle. ds0, ds1 disk drive select ds1 ds0 drive selected 0 0 drive 0 0 1 drive 1 dtl special sector size by setting n to zero (00), dtl ma y be used to control the number of bytes transferred in disk read/write commands. the sector size (n = 0) is set to 128. if the actual se ctor (on the diskette) is larger than dtl, the remainder of t he actual sector is r ead but is not passed to the host during read commands; during write commands, the remainder of the actual sector is wr itten with all zero bytes. the crc check code is calculated with the ac tual sector. when n is not zero, dtl has no meaning and should be set to ff hex. ec enable count when this bit is "1" t he "dtl" parameter of the verify command becomes sc (number of sectors per track). efifo enable fifo this active low bit when a 0, enables the fifo. a "1" disables the fifo (default). eis enable implied seek when set, a seek operation will be performed before executing any read or write command that requi res the c parameter in the command phase. a "0" disables the implied seek. eot end of track the final sector number of the current track. gap alters gap 2 length when using perpendicular mode. gpl gap length the gap 3 size. (gap 3 is the space between sectors excluding the vco synchronization field). h/hds head address selected head: 0 or 1 (di sk side 0 or 1) as encoded in the sector id field. hlt head load time the time interval that fdc waits after loading the head and before initializing a read or write operation. refer to the specify command for actual delays. hut head unload time the time interval from t he end of the execution phase (of a read or write command) until the head is unloaded. refer to the specify command for actual delays. downloaded from: http:///
39 symbol name description lock lock defines whether efifo, fi fothr, and pretrk parameters of the configure command can be reset to their default values by a "software reset". (a reset caused by writing to the appropriate bits of either the dsr or dor) mfm mfm/fm mode selector a one selects the double density (mfm) mode. a zero selects single density (fm) mode. mt multi-track selector when set, this flag selects the multi-track operating mode. in this mode, the fdc treats a complete cylinder under head 0 and 1 as a single track. the fdc operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. with this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the fdc finishes operating on the last sector under head 0. n sector size code this specifies the number of bytes in a sector. if this parameter is "00", then the sector size is 128 bytes. the number of bytes transferred is determined by the dt l parameter. otherwise the sector size is (2 raised to the "n'th" power) times 128. all values up to "07" hex are allowable. "07"h would equal a sector size of 16k. it is the user's responsibility to not select combinations that are not possible with the drive. n sector size 0 128 bytes 1 256 bytes 2 512 bytes 3 1024 bytes ncn new cylinder number the desired cylinder number. nd non-dma mode flag when set to 1, indicates that the fdc is to operate in the non-dma mode. in this mode, the host is interrupted for each data transfer. when set to 0, the fdc operates in dma mode, interfacing to a dma controller by means of t he drq and ndack signals. ow overwrite the bits d0-d3 of t he perpendicular mode command can only be modified if ow is set to 1. ow id defined in the lock command. pcn present cylinder number the current position of the head at the completi on of sense interrupt status command. poll polling disable when set, the internal polli ng routine is disabled. when clear, polling is enabled. pretrk precompensation start track number programmable from track 00 to ffh. r sector address the sector number to be read or written. in multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written. rcn relative cylinder number relative cylinder offset from present cylinder as used by the relative seek command. downloaded from: http:///
40 symbol name description sc number of sectors per track the number of sectors per track to be initialized by the format command. the number of sectors per track to be verified during a verify command when ec is set. sk skip flag when set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of read data. if read deleted is executed, only sectors with a deleted address mark will be accessed. when set to "0", the sect or is read or written the same as the read and write commands. srt step rate interval the time interval between step pulses issued by the fdc. programmable from 0.5 to 8 milliseco nds in increments of 0.5 ms at the 1 mbit data rate. refer to the specify command for actual delays. st0 st1 st2 st3 status 0 status 1 status 2 status 3 registers within the fdc which store status information after a command has been executed. this status information is available to the host during the result phas e after command execution. wgate write gate alters timing of we to allow for pre-erase loads in perpendicular drives. downloaded from: http:///
41 instruction set table 21 - instruction set read data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 0 0 1 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w -------- c -------- sector id information prior to command execution. w -------- h -------- w -------- r -------- w -------- n -------- w ------- eot ------- w ------- gpl ------- w ------- dtl ------- execution data transfer between the fdd and system. result r ------- st0 ------- status information after com- mand execution. r ------- st1 ------- r ------- st2 ------- r -------- c -------- sector id information after command execution. r -------- h -------- r -------- r -------- r -------- n -------- downloaded from: http:///
42 read deleted data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 0 1 1 0 0 command codes w 0 0 0 0 0 hds ds1 ds0 w -------- c -------- sector id information prior to command execution. w -------- h -------- w -------- r -------- w -------- n -------- w ------- eot ------- w ------- gpl ------- w ------- dtl ------- execution data transfer between the fdd and system. result r ------- st0 ------- status information after com- mand execution. r ------- st1 ------- r ------- st2 ------- r -------- c -------- sector id information after command execution. r -------- h -------- r -------- r -------- r -------- n -------- downloaded from: http:///
43 write data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm 0 0 0 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w -------- c -------- sector id information prior to command execution. w -------- h -------- w -------- r -------- w -------- n -------- w ------- eot ------- w ------- gpl ------- w ------- dtl ------- execution data transfer between the fdd and system. result r ------- st0 ------- status information after com- mand execution. r ------- st1 ------- r ------- st2 ------- r -------- c -------- sector id information after command execution. r -------- h -------- r -------- r -------- r -------- n -------- downloaded from: http:///
44 write deleted data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm 0 0 1 0 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w -------- c -------- sector id information prior to command execution. w -------- h -------- w -------- r -------- w -------- n -------- w ------- eot ------- w ------- gpl ------- w ------- dtl ------- execution data transfer between the fdd and system. result r ------- st0 ------- status information after command execution. r ------- st1 ------- r ------- st2 ------- r -------- c -------- sector id information after command execution. r -------- h -------- r -------- r -------- r -------- n -------- downloaded from: http:///
45 read a track data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 0 0 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w -------- c -------- sector id information prior to command execution. w -------- h -------- w -------- r -------- w -------- n -------- w ------- eot ------- w ------- gpl ------- w ------- dtl ------- execution data transfer between the fdd and system. fdc reads all of cylinders' contents from index hole to eot. result r ------- st0 ------- status information after command execution. r ------- st1 ------- r ------- st2 ------- r -------- c -------- sector id information after command execution. r -------- h -------- r -------- r -------- r -------- n -------- downloaded from: http:///
46 verify data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 1 0 1 1 0 command codes w ec 0 0 0 0 hds ds1 ds0 w -------- c -------- sector id information prior to command execution. w -------- h -------- w -------- r -------- w -------- n -------- w ------- eot ------- w ------- gpl ------- w ------ dtl/sc ------ execution no data transfer takes place. result r ------- st0 ------- status information after command execution. r ------- st1 ------- r ------- st2 ------- r -------- c -------- sector id information after command execution. r -------- h -------- r -------- r -------- r -------- n -------- version data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 0 0 command code result r 1 0 0 1 0 0 0 0 enhanced controller downloaded from: http:///
47 format a track data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 1 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w -------- n -------- bytes/sector w -------- sc -------- sectors/cylinder w ------- gpl ------- gap 3 w -------- d -------- filler byte execution for each sector repeat: w -------- c -------- input sector parameters w -------- h -------- w -------- r -------- w -------- n -------- fdc formats an entire cylinder result r ------- st0 ------- status information after command execution r ------- st1 ------- r ------- st2 ------- r ------ undefined ------ r ------ undefined ------ r ------ undefined ------ r ------ undefined ------ downloaded from: http:///
48 recalibrate data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 1 1 1 command codes w 0 0 0 0 0 0 ds1 ds0 execution head retracted to track 0 interrupt. sense interrupt status data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 0 0 0 command codes result r ------- st0 ------- status information at the end of each seek operation. r ------- pcn ------- specify data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 0 1 1 command codes w --- srt --- --- hut --- w ------ hlt ------ nd downloaded from: http:///
49 sense drive status data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 1 0 0 command codes w 0 0 0 0 0 hds ds1 ds0 result r ------- st3 ------- status information about fdd seek data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 1 1 1 command codes w 0 0 0 0 0 hds ds1 ds0 w ------- ncn ------- execution head positioned over proper cylinder on diskette. configure data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 1 1 configure information w 0 0 0 0 0 0 0 0 w 0 eis efifo poll --- fifothr --- execution w --------- pretrk --------- downloaded from: http:///
50 relative seek data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 1 dir 0 0 1 1 1 1 w 0 0 0 0 0 hds ds1 ds0 w ------- rcn ------- dumpreg data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 1 1 0 *note: registers placed in fifo execution result r ------ pcn-drive 0 ------- r ------ pcn-drive 1 ------- r ------ pcn-drive 2 ------- r ------ pcn-drive 3 ------- r ---- srt ---- --- hut --- r ------- hlt ------- nd r ------- sc/eot ------- r lock 0 d3 d2 d1 d0 gap wgate r 0 eis efifo poll -- fifothr -- r -------- pretrk -------- downloaded from: http:///
51 read id data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 1 0 1 0 commands w 0 0 0 0 0 hds ds1 ds0 execution the first correct id information on the cylinder is stored in data register result r -------- st0 -------- status information after command execution. disk status after the command has completed r -------- st1 -------- r -------- st2 -------- r -------- c -------- r -------- h -------- r -------- r -------- r -------- n -------- downloaded from: http:///
52 perpendicular mode data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 1 0 command codes ow 0 d3 d2 d1 d0 gap wgate invalid codes data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w ----- invalid codes ----- invalid command codes (noop - fdc goes into stand- by state) result r ------- st0 ------- st0 = 80h lock data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w lock 0 0 1 0 1 0 0 command codes result r 0 0 0 lock 0 0 0 0 sc is returned if the last command that was issued wa s the format command. eot is returned if the last command was a read or write. note: these bits are used internally only. they are not reflected in the drive select pins. it is the user's responsibility to maintain correspondence between t hese bits and the drive select pins (dor). downloaded from: http:///
53 data transfer commands all of the read data, write data and verify type commands use the same parameter bytes and return the same result s information, the only difference being the coding of bits 0-4 in the first byte. an implied seek will be ex ecuted if the feature was enabled by the configure co mmand. this seek is completely transparent to the user. the drive busy bit for the drive will go active in the main status register during the seek portion of the command. if the seek portion fails, it is reflected in the results status normally returned for a read/write data command. status register 0 (st0) would contain the error code and c would contain the cylinder on which the seek failed. read data a set of nine (9) bytes is required to place the fdc in the read data mode. after the read data command has been issued, the fdc loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the specify command), and begins reading id address marks and id fields. when the sector address read off the diskette matches with the sector address specified in the command, the fdc reads the sector's data fi eld and transfers the data to the fifo. after completion of the read operation from the current sector, the sector address is incremented by one and the data from the next logical sector is read and output via the fifo. this continuous read function is called "multi-sector read operation". upon receipt of tc, or an implied tc (fifo overrun/underrun), the fdc stops sending data but will continue to r ead data from the current sector, check the crc byte s, and at the end of the sector, terminate the read data command. n determines the number of bytes per sector (see table 21 below). if n is set to zero, the sector size is set to 128. the dtl value determines the number of bytes to be transferred. if dtl is less than 128, the fdc transfers the specified number of bytes to the host. for reads, it continues to read the entire 128-byte sector and checks for crc errors. for writes, it completes the 128-byte sector by filling in zeros. if n is not set to 00 hex, dtl should be set to ff hex and has no impact on the number of bytes transferred. table 22 - sector sizes the amount of data which can be handled with a single command to the fdc depends upon mt (multi-track) and n (number of bytes/sector). the multi-track function (mt) allows the fdc to read data from both sides of the diskette. for a particular cylinder, data will be transferred starting at sector 1, side 0 and co mpleting the last sector of the same track at side 1. if the host terminates a read or write operation in the fdc, the id information in the result phase is dependent upon the state of the mt bit and eot byte. refer to table 20. at the completion of the read data command, the head is not unloaded until after the head unload time interval (specified in the specify command) n sector size 00 01 02 03 .. 07 128 bytes 256 bytes 512 bytes 1024 bytes ... 16 kbytes downloaded from: http:///
54 has elapsed. if the host issues another command before the head unloads , then the head settling time may be saved between subsequent reads. if the fdc detects a pul se on the nindex pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the fdc sets the ic code in status register 0 to "01" indicating abnormal termination, sets the nd bit in status register 1 to "1" indicating a sector not found, and terminates the read data command. after reading the id and data fields in each sector, the fdc checks the crc bytes. if a crc error occurs in the id or data field, the fdc sets the ic code in status register 0 to "01" indicating abnormal termination, sets the de bit flag in status register 1 to "1", sets t he dd bit in status register 2 to "1" if crc is incorrect in the id field, and terminates the read data command. table 21 describes the effect of the sk bit on the read data command execution and results. except where noted in table 21, the c or r value of the sector address is automat ically incremented (see table 23). table 24 - effects of mt and n bits mt n maximum transfer capacity final sector read from disk 0 1 0 1 0 1 1 1 2 2 3 3 256 x 26 = 6,656 256 x 52 = 13,312 512 x 15 = 7,680 512 x 30 = 15,360 1024 x 8 = 8,192 1024 x 16 = 16,384 26 at side 0 or 1 26 at side 1 15 at side 0 or 1 15 at side 1 8 at side 0 or 1 16 at side 1 downloaded from: http:///
55 table 25 - skip bit vs read data command sk bit value data address mark type encountered results sector read? cm bit of st2 set? description of results 0 0 1 1 normal data deleted data normal data deleted data yes yes yes no no yes no yes normal termination. address not incremented. next sector not searched for. normal termination. normal termination. sector not read ("skipped"). downloaded from: http:///
56 read deleted data this command is the same as the read data command, only it operates on sectors that contain a deleted data address mark at the beginning of a data field. table 22 describes the effect of the sk bit on the read deleted data command execution and results. except where noted in table 22, the c or r value of the sector address is automatically incremented (see table 23). table 26 - skip bit vs. read deleted data command sk bit value data address mark type encountered results sector read? cm bit of st2 set? description of results 0 0 1 1 normal data deleted data normal data deleted data yes yes no yes yes no yes no address not incremented. next sector not searched for. normal termination. normal termination. sector not read ("skipped"). normal termination. downloaded from: http:///
57 read a track this command is similar to the read data command except that the entire data field is read continuously from each of t he sectors of a track. immediately after encount ering a pulse on the nindex pin, the fdc starts to read all data fields on the track as continuous blocks of data without regard to logical sector numbers. if the fdc finds an error in the id or data crc check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the command. the fdc compares the id information read from each sector with the s pecified value in the command and sets the nd flag of status register 1 to a "1" if there is no co mparison. multi-track or skip operations are not allowed with this command. the mt and sk bits (bits d7 and d5 of the first command byte respectively) should always be set to "0". this command terminates w hen the eot specified number of sectors has not been read. if the fdc does not find an id address mark on the diskette after the second occurrence of a pulse on the idx pin, then it sets the ic c ode in status register 0 to "01" (abnormal termination), sets the ma bit in status register 1 to "1", and terminates the command. table 27 - result phase mt head final sector transferred to id information at result phase host c h r n 0 0 less than eot nc nc r + 1 nc equal to eot c + 1 nc 01 nc 1 less than eot nc nc r + 1 nc equal to eot c + 1 nc 01 nc 1 0 less than eot nc nc r + 1 nc equal to eot nc lsb 01 nc 1 less than eot nc nc r + 1 nc equal to eot c + 1 lsb 01 nc nc: no change, the same value as the one at the beginning of command execution. lsb: least significant bit, t he lsb of h is complemented. downloaded from: http:///
58 write data after the write data command has been issued, the fdc loads the head (if it is in the unloaded state), waits the specif ied head load time if unloaded (defined in the sp ecify command), and begins reading id fields. when the sector address read from the diskette matches the sector address specified in the command, the fdc reads the data from the host via the fifo and writes it to the sector's data field. after writing data into the current sector, the fdc computes the crc value and writes it into the crc field at the end of th e sector transfer. the sector number stored in "r" is incremented by one, and the fdc continues writing to the next data field. the fdc continues this "multi-sector write operation". upon receipt of a terminal count signal or if a fifo over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. the fdc reads the id field of each sector and checks the crc bytes. if it detects a crc error in one of the id fields, it sets the ic code in status register 0 to "01" (abnormal termination), sets the de bit of status register 1 to "1 ", and terminates the write data command. the write data command operates in much the same manner as the read data command. the following items are the same. please refer to the read data command for details: ? transfer capacity ? en (end of cylinder) bit ? nd (no data) bit ? head load, unload time interval ? id information when the host terminates the command ? definition of dtl when n = 0 and when n does not = 0 write deleted data this command is almost the same as the write data command except that a deleted data address mark is written at the beginning of the data field instead of the normal data address mark. this command is typically used to mark a bad sector containing an error on the floppy disk. verify the verify command is used to verify the data stored on a disk. this command acts exactly like a read data command exc ept that no data is transferred to the host. data is read from the disk and crc is computed and checked against the previously-stored value. because data is not transferred to the host, tc (pin 89) cannot be used to terminate this command. by setting the ec bit to "1", an implicit tc will be issued to the fdc. this implicit tc will occur when the sc value has decremented to 0 (an sc value of 0 will verify 256 sectors). this command can also be terminated by setting the ec bit to "0" and the eot value equal to the final sector to be checked. if ec is set to "0", dtl/sc should be programmed to 0ffh. refer to table 23 and table 24 for information concerning the values of mt and ec versus sc and eot value. definitions: # sectors per side = number of formatted sectors per each side of the disk. # sectors remaining = number of formatted sectors left which can be read, including side 1 of the disk if mt is set to "1". downloaded from: http:///
59 table 28 - verify command result phase mt ec sc/eot value termination result 0 0 sc = dtl eot # sectors per side success termination result phase valid 0 0 sc = dtl eot > # sectors per side unsuccessful termination result phase invalid 0 1 sc # sectors remaining and eot # sectors per side successful termination result phase valid 0 1 sc > # sectors remaining or eot > # sectors per side unsuccessful termination result phase invalid 1 0 sc = dtl eot # sectors per side successful termination result phase valid 1 0 sc = dtl eot > # sectors per side unsuccessful termination result phase invalid 1 1 sc # sectors remaining and eot # sectors per side successful termination result phase valid 1 1 sc > # sectors remaining or eot > # sectors per side unsuccessful termination result phase invalid note: if mt is set to "1" and the sc value is gr eater than the number of rema ining formatted sectors on side 0, verifying will continue on side 1 of the disk. format a track the format command allows an entire track to be formatted. after a pulse from the idx pin is detected, the fdc starts writing data on the disk including gaps, address marks, id fields, and data fields per the ibm system 34 or 3740 format (mfm or fm respectively). the particular values that will be written to the gap and data field are controlled by the values programmed into n, sc, gpl, and d which are specified by the host during the command phase. the data field of the sector is filled with the data byte specified by d. the id field for each sector is supplied by the host; that is, four data bytes per sector are needed by the fdc for c, h, r, and n (cylinder , head, sector number and sector size respectively). after formatting each sect or, the host must send new values for c, h, r and n to the fdc for the next sector on the track. the r value (sector number) is the only value that must be changed by the host after each sector is formatted. this allows the disk to be formatted with nonsequential sector addresses (interleav ing). this incrementing and formatting continues for the whole track until the fdc encounters a pulse on the idx pin again and it terminates the command. table 25 contains typical values for gap fields which are dependent upon the si ze of the sector and the number of sectors on each track. actual values can vary due to drive electronics. downloaded from: http:///
60 format fields system 34 (double density) format gap4a 80x 4e sync 12x 00 iam gap1 50x 4e sync 12x 00 idam c y l hd s e c n o cr c gap2 22x 4e sync 12x 00 data am data c r c gap3 gap 4b 3x c2 fc 3x a1 fe 3x a1 fb f8 system 3740 (single density) format gap4a 40x ff sync 6x 00 iam gap1 26x ff sync 6x 00 idam c y l hd s e c n o cr c gap2 11x ff sync 6x 00 data am data c r c gap3 gap 4b fc fe fb or f8 perpendicular format gap4a 80x 4e sync 12x 00 iam gap1 50x 4e sync 12x 00 idam c y l hd s e c n o cr c gap2 41x 4e sync 12x 00 data am data c r c gap3 gap 4b 3x c2 fc 3x a1 fe 3x a1 fb f8 downloaded from: http:///
61 table 29 - typical values for formatting format sector size n sc gpl1 gpl2 5.25" drives fm 128 128 512 1024 2048 4096 ... 00 00 02 03 04 05 ... 12 10 08 04 02 01 07 10 18 46 c8 c8 09 19 30 87 ff ff mfm 256 256 512* 1024 2048 4096 ... 01 01 02 03 04 05 ... 12 10 09 04 02 01 0a 20 2a 80 c8 c8 0c 32 50 f0 ff ff 3.5" drives fm 128 256 512 0 1 2 0f 09 05 07 0f 1b 1b 2a 3a mfm 256 512** 1024 1 2 3 0f 09 05 0e 1b 35 36 54 74 gpl1 = suggested gpl values in read and write commands to avoid splice point between data field and id fiel d of contiguous sections. gpl2 = suggested gpl value in format a track command. *pc/at values (typical) **ps/2 values (typical). applies with 1.0 mb and 2.0 mb drives. note: all values except sector size are in hex. downloaded from: http:///
62 control commands control commands differ from the other commands in that no data transfer takes place. three commands generate an interrupt when complete: read id, reca librate, and seek. the other control commands do not generate an interrupt. read id the read id command is used to find the present position of the recording heads. the fdc stores the values from the first id field it is able to read into its registers. if the fdc does not find an id address mark on the diskette after the second occurrence of a pulse on the nindex pin, it then sets the ic code in status register 0 to "01" (abnormal termination), sets the ma bit in status register 1 to "1", and terminates the command. the following commands will generate an interrupt upon completion. they do not return any result bytes. it is highly recommended that control commands be followed by the sense interrupt status command. otherwi se, valuable interrupt status information will be lost. recalibrate this command causes the read/write head within the fdc to retract to the track 0 position. the fdc clears the contents of the pcn counter and checks the status of the ntr0 pin from the fdd. as long as the ntr0 pin is low, the dir pin remains 0 and step pulses are issued. when the ntr0 pin goes high, the se bit in status register 0 is set to "1" and the command is terminated. if the ntr0 pin is still low after 79 step pulses have been issued, the fdc sets the se and the ec bits of status register 0 to "1" and terminates the command. disks capable of handling more than 80 tracks per side may require more than one recalibrate command to return the head back to physical track 0. the recalibrate command does not have a result phase. the sense interrupt status command must be issued after the recalibrate command to effectively terminate it and to provide verification of the head position (pcn). during the command phase of the recalibrate oper ation, the fdc is in the busy state, but duri ng the execution phase it is in a non-busy state. at this time, another recalibrate command may be issued, and in this manner parallel recalibrate operations may be done on up to four drives at once. upon power up, the software must issue a recalibrate command to properly initialize all drives and the controller. seek the read/write head within t he drive is moved from track to track under the control of the seek command. the fdc compar es the pcn, which is the current head position, with the ncn and performs the following operation if there is a difference: pcn < ncn: direction signal to drive set to "1" (step in) and is pcn > ncn: direction signal to drive set to "0" (step out) and i the rate at which step pulses are issued is controlled by srt (stepping rate time) in the specify command. after each step pulse is issued, ncn is compared against pcn, and when ncn = pcn the se bit in status register 0 is set to "1" and the command is terminated. during the command phase of the seek or recalibrate operation, the fdc is in the busy state, but during the execution phase it is in the non-busy state. at this time, another seek or recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once. note that if implied s eek is not enabled, the read and write commands should be preceded by: 1) seek command - step to the proper track 2) sense interrupt status command - terminate the seek command 3) read id - verify head is on proper track 4) issue read/write command. the seek command does not have a result phase. therefore, it is high ly recommended that the downloaded from: http:///
63 sense interrupt status command is issued after the seek command to terminate it and to provide verification of the head position (pcn). the h bit (head address) in st0 will always return to a "0". when exiting powerdo wn mode, the fdc clears the pcn value and the status information to zero. prior to issuing the powerdown command, it is highly re commended that the user service all pending interrupts through the sense interrupt status command. sense interrupt status an interrupt signal on fint pin is generated by the fdc for one of the following reasons: 1. upon entering the result phase of: a. read data command b. read a track command c. read id command d. read deleted data command e. write data command f. format a track command g. write deleted data command h. verify command 2. end of seek, relative seek, or recalibrate command 3. fdc requires a data transfer during the execution phase in the non-dma mode the sense interrupt status command resets the interrupt signal and, via the ic code and se bit of status register 0, iden tifies the cause of the interrupt. interrupt identification the seek, relative seek, and recalibrate commands have no result phase. the sense interrupt status command must be issued immediately after these commands to terminate them and to provide verification of the head position (pcn). the h (head address) bit in st0 will always return a "0". if a sense interrupt status is not issued, the driv e will continue to be busy and may affect the operation of the next command. sense drive status sense drive status obt ains drive status information. it has not execution phase and goes directly to the result phase from the command phase. status register 3 contains the drive status information. specify the specify command sets the initial values for each of the three internal times. the hut (head unload time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. the srt (step rate time) defines the time interval between adjacent step pulses. no te that the spacing between the first and second step pulses may be shorter than the remaining step pulses. the hlt (head load time) defines the time between when the head load signal goes high and the read/write operation starts. the val ues change with the data rate speed selection and are documented in table 29. the values are the same for mfm and fm. table 30 - drive control delays (ms) se ic interrupt due to 0 1 1 11 00 01 polling normal termination of seek or recalibrate command abnormal termination of seek or recalibrate command downloaded from: http:///
11 hut srt 2m 1m 500k 300k 250k 2m 1m 500k 300k 250k 0 1 .. e f 64 4 .. 56 60 128 8 .. 112 120 256 16 .. 224 240 426 26.7 .. 373 400 512 32 .. 448 480 4 3.75 .. 0.5 0.25 8 7.5 .. 1 0.5 16 15 .. 2 1 26.7 25 .. 3.33 1.67 32 30 .. 4 2 hlt 2m 1m 500k 300k 250k 00 01 02 .. 7f 7f 64 0.5 1 .. 63 63.5 128 1 2 .. 126 127 256 2 4 .. 252 254 426 3.3 6.7 .. 420 423 512 4 8 . 504 508 the choice of dma or non-dma operations is made by the nd bit. when this bit is "1", the non- dma mode is selected, an d when nd is "0", the dma mode is selected. in dma mode, data transfers are signaled by the fdrq pin. non-dma mode uses the rqm bit and the fint pin to signal data transfers. configure the configure command is issued to select the special features of t he fdc. a configure command need not be issued if the default values of the fdc meet the system requirements. configure default values: eis - no implied seeks efifo - fifo disabled poll - polling enabled fifothr - fifo threshold set to 1 byte pretrk - pre-compensation set to track 0 eis - enable implied seek. when set to "1", the fdc will perform a seek operation before executing a read or write command. defaults to no implied seek. efifo - a "1" disables the fifo (default). this means data transfers are asked for on a byte-by- byte basis. defaults to "1", fifo disabled. the threshold defaults to "1". poll - disable polling of the drives. defaults to "0", polling enabled. when enabled, a single interrupt is generated after a reset. no polling is performed while the drive head is loaded and the head unload delay has not expired. fifothr - the fifo threshold in the execution phase of read or writ e commands. this is programmable from 1 to 16 bytes. defaults to one byte. a "00" selects one byte; "0f" selects 16 bytes. pretrk - pre-compensation start track number. programmable from track 0 to 255. defaults to track 0. a "00" selects track 0; "ff" selects track 255. version the version command checks to see if the controller is an enhanced type or the older type (765a). a value of 90 h is returned as the result byte. downloaded from: http:///
65 relative seek the command is coded the same as for seek, except for the msb of t he first byte and the dir bit. dir action 0 1 step head out step head in dir head step direction control rcn relative cylinder number that determines how many tracks to step the head in or out from the current track number. the relative seek command differs from the seek command in that it st eps the head the absolute number of tracks spec ified in the command instead of making a comparison against an internal register. the seek command is good for drives that support a maximum of 256 tracks. relative seeks cannot be overlapped with other relative seeks. only one relative seek can be active at a time. relative seeks may be overlapped with seeks and recalibrates. bit 4 of status register 0 (ec) will be set if relative seek attempts to step outward beyond track 0. as an example, assume that a floppy drive has 300 useable tracks. the host needs to read track 300 and the head is on any track (0-255). if a seek command is issued, the head will stop at track 255. if a relative seek command is issued, the fdc will move the head the specified number of tracks, regardless of the internal cylinder position register (but will increment the register). if the head was on track 40 (d), the maximum track that the fdc could position the head on using relative seek will be 295 (d), the initial track + 255 (d). the maximum count that the head can be moved with a single relative seek command is 255 (d). the internal register, p cn, will overflow as the cylinder number crosses track 255 and will contain 39 (d). the resulting pcn value is thus (rcn + pcn) mod 256. functionally, the fdc starts counting from 0 again as the track number goes above 255 (d). it is the user's responsibility to compensate fdc functions (precompensation track number) when accessing tracks greater than 255. the fdc does not ke ep track that it is working in an "extended track area" (greater than 255). any command issued will use the current pcn value except for the recalibrate command, which only looks for the track0 signal. recalibrate will return an error if the head is farther than 79 due to its limitation of issuing a maximum of 80 step pulses. the user simply needs to issue a second recalibrate command. the seek command and implied seeks will function correctly within the 44 (d) track (299-255) area of the "extended track area". it is the user's responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area. to return to the standard floppy range (0-255) of tracks, a relative seek should be issued to cross the track 255 boundary. a relative seek can be used instead of the normal seek, but the host is required to calculate the difference between the current head location and the new (target) head location. this may require the host to issue a read id command to ensure that the head is physica lly on the track that software assumes it to be. different fdc commands will return different cylinder results which may be difficult to keep track of with software without the read id command. perpendicular mode the perpendicular mode command should be issued prior to executing read/write/format commands that access a disk drive with perpendicular recording capability. with this command, the length of the gap2 field and vco enable timing can be altered to accommodate the unique requirements of these drives. table 28 describes the effects of the wgate and gap bits for the perpendicular mode command. upon a reset, the fdc will default to the conventional mode (wgate = 0, gap = 0). selection of the 500 kbps and 1 mbps perpendicular modes is independent of the actual downloaded from: http:///
66 data rate selected in the data rate select register. the user must ensure that these two data rates remain consistent. the gap2 and vco timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. in the design of this head, a pre-erase head precedes the normal read/write head by a distanc e of 200 micrometers. this works out to about 38 bytes at a 1 mbps recording density. whenever the write head is enabled by the write gate signal, the pre-erase head is also activated at the same time. thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-erase head since it has not yet been activated. to accommodate this head activation and deactivation time, the gap2 field is expanded to a length of 41 bytes. the format field shown on page 58 illustrates the change in the gap2 field size for the perpendicular format. on the read back by the f dc, the controller must begin synchronization at t he beginning of the sync field. for the conventional mode, the internal pll vco is enabled (vcoen) approximately 24 bytes from the start of the ga p2 field. but, when the controller operates in t he 1 mbps perpendicular mode (wgate = 1, gap = 1), vcoen goes active after 43 bytes to accommodate the increased gap2 field size. for both cases, and approximate two-byte cushion is maintained from the beginning of the sync fi eld for the purposes of avoiding write splices in the presence of motor speed variation. for the write data case, the fdc activates write gate at the beginning of the sync field under the conventional mode. the controller then writes a new sync field, data address mark, data field, and crc as shown on page 57. with the pre-erase head of the perpendicular drive, the write head must be activated in the gap2 field to insure a proper write of the new sync field. for the 1 mbps perpendicular mode (wgate = 1, gap = 1), 38 bytes will be written in t he gap2 space. since the bit density is proportional to the data rate, 19 bytes will be written in the gap2 field for the 500 kbps perpendicular mode (wgate = 1, gap =0). it should be noted that none of the alterations in gap2 size, vco timing, or write gate timing affect normal program flow. the information provided here is just for background purposes and is not needed for normal operation. once the perpendicular mode command is invoked, fdc software behavior from the user standpoint is unchanged. the perpendicular mode command is enhanced to allow specific drives to be designated perpendicular recording drives. this enhancement allows data transfers between conventional and perpendicular drives without having to issue perpendicular mode commands between the accesses of the different drive types, nor having to change write pre-compensation values. when both gap and wgate bits of the perpendicular mode command are both programmed to "0" (conventional mode), then d0, d1, d2, d3, and d4 can be programmed independently to "1" for that drive to be set automatically to perpendicul ar mode. in this mode the following set of conditions also apply: 1. the gap2 written to a perpendicular drive during a write operation will depend upon the programmed data rate. 2. the write pre-compensation given to a perpendicular mode drive will be 0ns. 3. for d0-d3 programmed to "0" for conventional mode drives any data written will be at the currently programmed write pre-compensation. note: bits d0-d3 can only be overwritten when ow is programmed as a "1".if either gap or wgate is a "1" then d0-d3 are ignored. software and hardware resets have the following effect on the perpendicular mode command: 1. "software" resets (via the dor or dsr registers) will only clear gap and wgate bits to "0". d0-d3 are unaffected and retain their previous value. downloaded from: http:///
67 2. "hardware" resets will clear all bits (gap, wgate and d0-d3) to "0", i.e all conventional mode. table 31 - effects of wgate and gap bits wgate gap mode length of gap2 format field portion of gap 2 written by write data operation 0 0 1 1 0 1 0 1 conventional perpendicular (500 kbps) reserved (conventional) perpendicular (1 mbps) 22 bytes 22 bytes 22 bytes 41 bytes 0 bytes 19 bytes 0 bytes 38 bytes downloaded from: http:///
68 lock in order to protect systems with long dma latencies against older application software that can disable the fifo the lock command has been added. this command should only be used by the fdc routines, and application software should refrain from using it. if an application calls for the fifo to be dis abled then the configure command should be used. the lock command defines whether the efifo, fifothr, and pretrk parameters of the configure command can be reset by the dor and dsr registers. when the lock bit is set to logic "1" all subsequent "software resets by the dor and dsr regi sters will not change the previously set parameters to their default values. all "hardware" reset from the reset pin will set the lock bit to logic "0" and return the efifo, fifothr, and pretrk to their default values. a status byte is returned immediately after issuing a lock command. this byte reflects the value of the lock bit set by the command byte. enhanced dumpreg the dumpreg command is designed to support system run-time diagnostics and application software development and debug. to accommodate the lock command and the enhanced perpendicular mode command the eighth byte of the dumpreg command has been modified to contain the additional data from these two commands. compatibility this chip was designed with software compatibility in mind. it is a fully backwards- compatible solution with the older generation 765a/b disk controllers. the fdc also implements on-board regist ers for compatibility with the ps/2, as well as pc/at and pc/xt, floppy disk controller subsystems. after a hardware reset of the fdc, all registers, functions and enhancements default to a pc/at, ps/2 or ps/2 model 30 compatible operating mode, depending on how the ident and mfm bits are configured by the system bios. force write protect the force write protect function forces the fdd nwrtprt input active if the force wrtprt bit is active. the force write protect function applies to the nwrtprt pin in the fdd interface as well as the nwrtprt pin in the parallel port fdc. refer to configuration register l8cr_c5 for more information. downloaded from: http:///
69 serial port (uart) the chip incorporates two full function uarts. they are compatible with the ns16450, the 16450 ace registers and the ns16c550a. the uarts perform serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. the data rates are independently programmable from 460.8k baud down to 50 baud. the character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. the uarts each contain a programmable baud rate gener ator that is capable of dividing the input clock or crystal by a number from 1 to 65535. the uarts are also capable of supporting the midi data rate. refer to the configuration registers for information on disabling, power down and changing the base address of the uarts. the interrupt from a uart is enabled by programming out2 of that uart to a logic "1". out2 being a logic "0" disables that uart's interrupt. the second uart also supports irda 1.0, hp-sir and ask-ir infrared modes of operation. note: the uarts may be configured to share an interrupt. refer to the configuration section for more information. register description addressing of the accessible registers of the serial port is shown below. th e configuration registers (see configuration sect ion) define the base addresses of the serial ports. the serial port registers are located at sequentially increasing addresses above these base addresses. the chip contains two serial ports , each of which contain a register set as described below. table 32 - addressing the serial port dlab* a2 a1 a0 register name 0 0 0 0 receive buffer (read) 0 0 0 0 transmit buffer (write) 0 0 0 1 interrupt enable (read/write) x 0 1 0 interrupt identification (read) x 0 1 0 fifo control (write) x 0 1 1 line control (read/write) x 1 0 0 modem control (read/write) x 1 0 1 line stat us (read/write) x 1 1 0 modem stat us (read/write) x 1 1 1 scratchpad (read/write) 1 0 0 0 divisor lsb (read/write) 1 0 0 1 divisor msb (read/write *note: dlab is bit 7 of the line control register the following section describes the operation of t he registers. downloaded from: http:///
70 receive buffer register (rb) address offset = 0h, dlab = 0, read only this register holds t he received incoming data byte. bit 0 is the least significant bit, which is transmitted and received first. received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the receive buffer register. the shift register is not accessible. transmit buffer register (tb) address offset = 0h, dlab = 0, write only this register contains the data byte to be transmitted. the transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. this shift register is loaded from the transmit buffer when the transmission of the previous byte is complete. interrupt enable register (ier) address offset = 1h, dlab = 0, read/write the lower four bits of th is register control the enables of the five interrupt sources of the serial port interrupt. it is possi ble to totally disable the interrupt system by resetting bits 0 through 3 of this register. similarly, setting the appropriate bits of this register to a hi gh, selected interrupts can be enabled. disabling the interrupt system inhibits the interrupt identificati on register and disables any serial port interrupt out of the chip. all other system functions operate in their normal manner, including the line stat us and modem status registers. the contents of the interrupt enable register are described below. bit 0 this bit enables the received data available interrupt (and timeout inte rrupts in the fifo mode) when set to logic "1". bit 1 this bit enables the transmitter holding register empty interrupt when set to logic "1". bit 2 this bit enables the received line status interrupt when set to logic "1". the error sources causing the interrupt are overrun, parity, framing and break. the line status register must be read to determine the source. bit 3 this bit enables the modem status interrupt when set to logic "1". this is caused when one of the modem status regist er bits changes state. bits 4 through 7 these bits are always logic "0". fifo control register (fcr) address offset = 2h, dlab = x, write this is a write only regist er at the same location as the iir. this register is used to enable and clear the fifos, set the rcvr fifo trigger level. note: dma is not supported. the uart1 and uart2 fcrs are shadowed in th e uart1 fifo control shadow register (ld8:crc3[7:0]) and uart2 fifo control shadow register (ld8:crc4[7:0]). bit 0 setting this bit to a logic "1" enables both the xmit and rcvr fifos. clearing this bit to a logic "0" disables both the xmit and rcvr fifos and clears all bytes from both fifos. when changing from fifo mode to non- fifo (16450) mode, data is automatically cleared fr om the fifos. this bit must be a 1 when other bits in this register are written to or they will not be properly programmed. bit 1 setting this bit to a logic "1" clears all bytes in the rcvr fifo and resets its counter logic to 0. the shift register is not cleared. this bit is self- clearing. downloaded from: http:///
71 bit 2 setting this bit to a logic "1" clears all bytes in the xmit fifo and resets its counter logic to 0. the shift register is not cleared. this bit is self- clearing. bit 3 writing to this bit has no effect on the operation of the uart. the rxrdy and txrdy pins are not available on this chip. bit 4,5 reserved bit 6,7 these bits are used to set the trigger level for the rcvr fifo interrupt. bit 7 bit 6 rcvr fifo trigger level (bytes) 0 0 1 0 1 4 1 0 8 1 1 14 interrupt identification register (iir) address offset = 2h, dlab = x, read by accessing this register, the host cpu can determine the highest priority interrupt and its source. four levels of priority interrupt exist. they are in descending order of priority: 1. receiver line status (highest priority) 2. received data ready 3. transmitter holding register empty 4. modem status (lowest priority) information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the interrupt identific ation register (refer to interrupt control table). when the cpu accesses the iir, the serial port freezes all interrupts and indicates the highest priority pending interrupt to the cpu. during this cpu access, even if the serial port records new interrupts, the current indication does not change until access is completed. the contents of the iir are described below. bit 0 this bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. when bit 0 is a logic "0", an interrupt is pending and the contents of the iir may be used as a pointer to the appropriate internal service routine. when bit 0 is a logic "1", no interrupt is pending. bits 1 and 2 these two bits of the iir are used to identify the highest priority interrupt pending as indicated by the interrupt control table. bit 3 in non-fifo mode, this bit is a logic "0". in fifo mode this bit is set along with bit 2 when a timeout interrupt is pending. bits 4 and 5 these bits of the iir are always logic "0". bits 6 and 7 these two bits are set when the fifo control register bit 0 equals 1. downloaded from: http:///
72 table 33 - interrupt control fifo mode only interrupt identification register interrupt set and reset functions bit 3 bit 2 bit 1 bit 0 priority level interrupt type interrupt source interrupt reset control 0 0 0 1 - none none - 0 1 1 0 highest receiver line status overrun error, parity error, framing error or break interrupt reading the line status register 0 1 0 0 second received data available receiver data available read receiver buffer or the fifo drops below the trigger level. 1 1 0 0 second character timeout indication no characters have been removed from or input to the rcvr fifo during the last 4 char times and there is at least 1 char in it during this time reading the receiver buffer register 0 0 1 0 third transmitter holding register empty transmitter holding register empty reading the iir register (if source of interrupt) or writing the transmitter holding register 0 0 0 0 fourth modem status clear to send or data set ready or ring indicator or data carrier detect reading the modem status register downloaded from: http:///
73 bit 2 word length number of stop bits 0 -- 1 1 5 bits 1.5 1 6 bits 2 1 7 bits 2 1 8 bits 2 line control register (lcr) address offset = 3h, dlab = 0, read/write this register contains the format information of the serial line. the bit definitions are: bits 0 and 1 these two bits specify the number of bits in each transmitted or received serial character. the encoding of bits 0 and 1 is as follows: the start, stop and parity bits are not included in the word length. bit 1 bit 0 word length 0 0 1 1 0 1 0 1 5 bits 6 bits 7 bits 8 bits bit 2 this bit specifies the num ber of stop bits in each transmitted or received serial character. the following table summarizes the information. note: the receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting. bit 3 parity enable bit. when bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. (the parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed). bit 4 even parity select bit. when bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is transmitted or checked in the data word bits and the parity bit. when bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked. bit 5 stick parity bit. when bit 3 is a logic "1" and bit 5 is a logic "1", the parity bit is transmitted and then detected by the receiver in the opposite state indicated by bit 4. bit 6 set break control bit. when bit 6 is a logic "1", the transmit data output (txd) is forced to the spacing or logic "0" state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. this feature enables the serial port to alert a terminal in a communications system. bit 7 divisor latch access bit (dlab). it must be set high (logic "1") to access the divisor latches of the baud rate generator during read or write operations. it must be set low (logic "0") to access the receiver buffer register, the transmitter holding register, or the interrupt enable register. downloaded from: http:///
74 modem control register (mcr) address offset = 4h, dlab = x, read/write this 8 bit register contro ls the interface with the modem or data set (or device emulating a modem). the contents of the modem control register are described below. bit 0 this bit controls the data terminal ready (ndtr) output. when bit 0 is set to a logic "1", the ndtr output is forced to a logic "0". when bit 0 is a logic "0", the ndtr output is forced to a logic "1". bit 1 this bit controls the request to send (nrts) output. bit 1 affects the nrts output in a manner identical to that described above for bit 0. bit 2 this bit controls the output 1 (out1) bit. this bit does not have an output pin and can only be read or written by the cpu. bit 3 output 2 (out2). this bit is used to enable an uart interrupt. when out2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. when out2 is a logic "1", the serial po rt interrupt outputs are enabled. bit 4 this bit provides the loopback feature for diagnostic testing of the serial port. when bit 4 is set to logic "1", the following occur: 1. the txd is set to the marking state(logic "1"). 2. the receiver serial input (rxd) is disconnected. 3. the output of the trans mitter shift register is "looped back" into the receiver shift register input. 4. all modem control inputs (ncts, ndsr, nri and ndcd) are disconnected. 5. the four modem co ntrol outputs (ndtr, nrts, out1 and out2) are internally connected to the four modem control inputs (ndsr, ncts, ri, dcd). 6. the modem control output pins are forced inactive high. 7. data that is trans mitted is immediately received. this feature allows the processor to verify the transmit and receive data paths of the serial port. in the diagnostic mode, the receiver and the transmitter interrupts are fully operational. the modem control interrupts are also operational but the interrupts' sources are now the lower four bits of the modem contro l register instead of the modem control inputs. the interrupts are still controlled by the interrupt enable register. bits 5 through 7 these bits are permanently set to logic zero. line status register (lsr) address offset = 5h, dlab = x, read/write bit 0 data ready (dr). it is set to a logic "1" whenever a complete incoming character has been received and transferred into the receiver buffer register or the fifo. bit 0 is reset to a logic "0" by reading all of the data in the receive buffer register or the fifo. bit 1 overrun error (oe). bit 1 indicates that data in the receiver buffer register was not read before the next character was transferred into the register, thereby destroying the previous character. in fifo mode, an overrun error will occur only when the fifo is full and the next character has been completely received in the shift register, the character in the shift regist er is overwritten but not transferred to the fifo. the oe indicator is set to a logic "1" immediately upon detection of an overrun condition, and reset whenever the line status register is read. bit 2 parity error (pe). bit 2 i ndicates that the received data character does not hav e the correct even or odd parity, as selected by the even parity select bit. the pe is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the line status register is read. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated characte r is at the top of the fifo. bit 3 downloaded from: http:///
75 framing error (fe). bit 3 indicates that the received character did not have a valid stop bit. bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (spacing level). the fe is reset to a logic "0" whenever the line status register is read. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. the serial port will try to resynchronize after a framing error. to do this, it assumes that the framing error was due to the next start bit, so it samples this 'start' bit twice and then takes in the 'data'. bit 4 break interrupt (bi). bit 4 is set to a logic "1" whenever the received data input is held in the spacing state (logic "0") for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). the bi is reset after the cpu reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. when break occurs only one zero character is loaded into the fifo. restarting after a break is received, requires the serial data (rxd) to be logic "1" for at least 1/2 bit time. note: bits 1 through 4 are the error conditions that produce a receiver li ne status interrupt whenever any of the corre sponding conditions are detected and the inte rrupt is enabled. bit 5 transmitter holding register empty (thre). bit 5 indicates that the serial port is ready to accept a new character for transmission . in addition, this bit causes the serial port to issue an interrupt when the transmitter holding register interrupt enable is set high. the thre bit is set to a logic "1" when a character is transferred from the transmitter holding register into the transmitter shift register. the bit is reset to logic "0" whenever the cpu loads the transmitter holding register. in the fifo mode this bit is set when the xmit fifo is empty, it is cleared when at least 1 byte is written to the xmit fifo. bit 5 is a read only bit. bit 6 transmitter empty (temt). bit 6 is set to a logic "1" whenever the transmitter holding register (thr) and transmitter shift register (tsr) are both empty. it is reset to logic "0" whenever either the thr or tsr contains a data character. bit 6 is a read only bit. in the fifo mode this bit is set whenever the thr and tsr are both empty, bit 7 this bit is permanently set to logic "0" in the 450 mode. in the fifo mode, this bit is set to a logic "1" when there is at least one parity error, framing error or break indication in the fifo. this bit is cleared when the lsr is read if there are no subsequent errors in the fifo. modem status register (msr) address offset = 6h, dlab = x, read/write this 8 bit register provides the current state of the control lines from the modem (or peripheral device). in addition to this current state information, four bits of the modem status register (msr) provide change information. these bits are set to logic "1" whenever a control input from the modem changes state. they are reset to logic "0" whenever the modem status register is read. downloaded from: http:///
76 bit 0 delta clear to send (dcts). bit 0 indicates that the ncts input to the chip has changed state since the last time the msr was read. bit 1 delta data set ready (ddsr). bit 1 indicates that the ndsr input has changed state since the last time the msr was read. bit 2 trailing edge of ring indicator (teri). bit 2 indicates that the nri i nput has changed from logic "0" to logic "1". bit 3 delta data carrier detect (ddcd). bit 3 indicates that the ndcd input to the chip has changed state. note: whenever bit 0, 1, 2, or 3 is set to a logic "1", a modem status in terrupt is generated. bit 4 this bit is the complement of the clear to send (ncts) input. if bit 4 of the mcr is set to logic "1", this bit is equivalent to nrts in the mcr. bit 5 this bit is the complement of the data set ready (ndsr) input. if bit 4 of the mcr is set to logic "1", this bit is equivalent to dtr in the mcr. bit 6 this bit is the complem ent of the ring indicator (nri) input. if bit 4 of the mcr is set to logic "1", this bit is equivalent to out1 in the mcr. bit 7 this bit is the complement of the data carrier detect (ndcd) input. if bit 4 of the mcr is set to logic "1", this bit is equival ent to out2 in the mcr. scratchpad register (scr) address offset =7h, dlab =x, read/write this 8 bit read/write regist er has no effect on the operation of the serial port. it is intended as a scratchpad register to be used by the programmer to hold data temporarily. programmable baud rate generator (and divisor latches dlh, dll) the serial port contains a programmable baud rate generator that is capable of taking any clock input (dc to 3 mhz) and dividing it by any divisor from 1 to 65535. this output frequency of the baud rate generator is 16x the baud rate. two 8 bit latches store the divisor in 16 bit binary format. these divisor latches must be loaded during initialization in order to insure desired operation of the baud rate generator. upon loading either of the divisor latches, a 16 bit baud counter is immediately loaded. this prevents long counts on initial load. if a 0 is loaded into the brg registers the output divides the clo ck by the number 3. if a 1 is loaded the output is the inverse of the input oscillator. if a two is loaded the output is a divide by 2 signal with a 50% duty cycle. if a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. the input clock to the brg is a 1.8462 mhz clock. table 31 shows the baud rates possible with a 1.8462 mhz crystal. downloaded from: http:///
77 table 34 - baud rates using 1.8462 mhz cl ock for <= 38.4k; using 1.8432mhz clock for 115.2k ; using 3.6864mhz clock for 230.4k; using 7.3728 mhz clock for 460.8k desired baud rate divisor used to generate 16x clock percent error difference between desired and actual 1 high speed bit 2 50 2304 0.001 x 75 1536 - x 110 1047 - x 134.5 857 0.004 x 150 768 - x 300 384 - x 600 192 - x 1200 96 - x 1800 64 - x 2000 58 0.005 x 2400 48 - x 3600 32 - x 4800 24 - x 7200 16 - x 9600 12 - x 19200 6 - x 38400 3 0.030 x 57600 2 0.16 x 115200 1 0.16 x 230400 32770 0.16 1 460800 32769 0.16 1 note 1 : the percentage error for all baud rates, exc ept where indicated otherwise, is 0.2%. note 2 : the high speed bit is located in the device configuration space. effect of the reset on register file the reset function table (table 35) details the effect of the reset input on each of the registers of the serial port. downloaded from: http:///
78 fifo interrupt mode operation when the rcvr fifo and receiver interrupts are enabled (fcr bit 0 = "1", ier bit 0 = "1"), rcvr interrupts occur as follows: a. the receive data available interrupt will be issued when the fifo has reached its programmed trigger level; it is cleared as soon as the fifo drops below its programmed trigger level. b. the iir receive data available indication also occurs when the fifo trigger level is reached. it is cleared when the fifo drops below the trigger level. c. the receiver line status interrupt (iir=06h), has higher priority than the received data available (iir=04h) interrupt. d. the data ready bit (lsr bit 0) is set as soon as a character is transferred from the shift register to the rcvr fifo. it is reset when the fifo is empty. when rcvr fifo and receiver interrupts are enabled, rcvr fifo timeout interrupts occur as follows: a. a fifo timeout interrupt occurs if all the following conditions exist: - at least one character is in the fifo. - the most recent serial character received was longer than 4 continuous character times ago. (if 2 stop bits are programmed, the second one is included in this time delay). - the most recent cpu read of the fifo was longer than 4 continuous character times ago. this will cause a maximum character received to interrupt issued delay of 160 msec at 300 baud with a 12 bit character. b. character times are calculated by using the rclk input for a clock signal (this makes the delay proportional to the baudrate). c. when a timeout interrupt has occurred it is cleared and the timer reset when the cpu reads one character from the rcvr fifo. d. when a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the cpu reads the rcvr fifo. when the xmit fifo and transmitter interrupts are enabled (fcr bit 0 = "1", ier bit 1 = "1"), xmit interrupts occur as follows: a. the transmitter holding register interrupt (02h) occurs when the xmit fifo is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the xmit fifo while servicing this interrupt) or the iir is read. b. the transmitter fifo empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: thre=1 and there have not been at least two bytes at the same time in the transmitter fifo since the last thre=1. the transmitter interrupt after changing fcr0 will be immediate, if it is enabled. character timeout and rcvr fifo trigger level interrupts have the same priority as the current received data available interrupt; xmit fifo empty has the same priority as the current transmitter holding register empty interrupt. downloaded from: http:///
79 fifo polled mode operation with fcr bit 0 = "1" resetting ier bits 0, 1, 2 or 3 or all to zero puts the uart in the fifo polled mode of operation. since the rcvr and xmitter are controlled separ ately, either one or both can be in the polled m ode of operation. in this mode, the user's program will check rcvr and xmitter status via the ls r. lsr definitions for the fifo polled mode are as follows: - bit 0=1 as long as there is one byte in the rcvr fifo. - bits 1 to 4 specify which error(s) have occurred. character error status is handled the same way as when in the interrupt mode, the iir is not affected since eir bit 2=0. - bit 5 indicates when the xmit fifo is empty. - bit 6 indicates that both the xmit fifo and shift register are empty. - bit 7 indicates whether there are any errors in the rcvr fifo. there is no trigger level reached or timeout condition indicated in the fifo polled mode, however, the rcvr and xmit fifos are still fully capable of holding characters. downloaded from: http:///
80 table 35 - reset function register/signal reset control reset state interrupt enable register reset all bits low interrupt identification reg. reset bit 0 is high; bits 1 - 7 low fifo control reset all bits low line control reg. reset all bits low modem control reg. reset all bits low line status reg. reset all bits low except 5, 6 high modem status reg. reset bits 0 - 3 low; bits 4 - 7 input txd1, txd2 reset high intrpt (rcvr errs) reset/read lsr low intrpt (rcvr data ready) reset/read rbr low intrpt (thre) reset/readiir/write thr low out2b reset high rtsb reset high dtrb reset high out1b reset high rcvr fifo reset/ fcr1*fcr0/_fcr0 all bits low xmit fifo reset/ fcr1*fcr0/_fcr0 all bits low downloaded from: http:///
81 table 36 - register summary for an individual uart channel register address* register name register symbol bit 0 bit 1 addr = 0 dlab = 0 receive buffer register (read only) rbr data bit 0 (note 1) data bit 1 addr = 0 dlab = 0 transmitter holding register (write only) thr data bit 0 data bit 1 addr = 1 dlab = 0 interrupt enable register ier enable received data available interrupt (erdai) enable transmitter holding register empty interrupt (ethrei) addr = 2 interrupt ident. register (read only) iir "0" if interrupt pending interrupt id bit addr = 2 fifo control register (write only) fcr (note 7) fifo enable rcvr fifo reset addr = 3 line control register lcr word length select bit 0 (wls0) word length select bit 1 (wls1) addr = 4 modem control register mcr data terminal ready (dtr) request to send (rts) addr = 5 line status register lsr data ready (dr) overrun error (oe) addr = 6 modem status register msr delta clear to send (dcts) delta data set ready (ddsr) addr = 7 scratch register (note 4) scr bit 0 bit 1 addr = 0 dlab = 1 divisor latch (ls) ddl bit 0 bit 1 addr = 1 dlab = 1 divisor latch (ms) dlm bit 8 bit 9 *dlab is bit 7 of the line control register (addr = 3). note 1: bit 0 is the least significant bit. it is the first bit serially transmitted or received. note 2: when operating in the xt mode, this bit will be set any time that the transmitter shift register is empty. downloaded from: http:///
82 table 37 - register summary for an individual uart channel (continued) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 enable receiver line status interrupt (elsi) enable modem status interrupt (emsi) 0 0 0 0 interrupt id bit interrupt id bit (note 5) 0 0 fifos enabled (note 5) fifos enabled (note 5) xmit fifo reset dma mode select (note 6) reserved reserved rcvr trigger lsb rcvr trigger msb number of stop bits (stb) parity enable (pen) even parity select (eps) stick parity set break divisor latch access bit (dlab) out1 (note 3) out2 (note 3) loop 0 0 0 parity error (pe) framing error (fe) break interrupt (bi) transmitter holding register (thre) transmitter empty (temt) (note 2) error in rcvr fifo (note 5) trailing edge ring indicator (teri) delta data carrier detect (ddcd) clear to send (cts) data set ready (dsr) ring indicator (ri) data carrier detect (dcd) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 note 3: this bit no longer has a pin associated with it. note 4: when operating in the xt mode , this register is not available. note 5: these bits are always zero in the non-fifo mode. note 6: writing a one to this bit has no effe ct. dma modes are not supported in this chip. note 7: the uart1 and uart2 fcrs are shadowed in the uart1 fifo co ntrol shadow register (ld8:crc3[7:0]) and uart2 fifo contro l shadow register (ld8:crc4[7:0]). downloaded from: http:///
83 notes on serial port operation fifo mode operation: general the rcvr fifo will hold up to 16 bytes regardless of which trigger level is selected. tx and rx fifo operation the tx portion of the uart transmits data through txd as soon as the cpu loads a byte into the tx fifo. the uart will prevent loads to the tx fifo if it currently holds 16 characters. loading to the tx fifo will again be enabled as soon as the next character is transferred to the tx shift register. these capabilities account for the largely autonomous oper ation of the tx. the uart starts the above operations typically with a tx interrupt. the chip issues a tx interrupt whenever the tx fifo is empty and the tx interrupt is enabled, except in the following instance. assume that t he tx fifo is empty and the cpu starts to load it. when the first byte enters the fifo the tx fi fo empty interrupt will transition from active to inactive. depending on the execution speed of the se rvice routine software, the uart may be able to transfer this byte from the fifo to the shift regi ster before the cpu loads another byte. if this happens, the tx fifo will be empty again and typically the uart's interrupt line would transition to the acti ve state. this could cause a system with an in terrupt control unit to record a tx fifo empty condition, even though the cpu is currently servicing that interrupt. therefore, after the first byte has been loaded into the fifo the uart will wait one serial character transmission time before issuing a new tx fifo empty interrupt. this one character tx interrupt delay will remain active until at least two bytes have the tx fifo empties after this condition, the tx been loaded into the fifo, concurrently. when interrupt will be activated without a one character delay. rx support functions and operation are quite different from those described for the transmitter. the rx fifo receives data until the number of bytes in the fifo equals the selected interrupt trigger level. at that time if rx interrupts are enabled, the uart will issue an interrupt to the cpu. the rx fifo will continue to store bytes until it holds 16 of them. it will not accept any more data when it is full. any more data entering the rx shift register will set the overrun error flag. normally, the fifo depth and the programmable trigger levels will give the cpu ample time to empty the rx fifo before an overrun occurs. one side-effect of having a rx fifo is that the selected interrupt trigger level may be above the data level in the fifo. this could occur when data at the end of the block contains fewer bytes than the trigger level. no interrupt would be issued to the cpu and the data would remain in the uart. to prevent the software from having to check for this situation the chip incorporates a timeout interrupt. the timeout interrupt is activated when there is a least one byte in the rx fifo, and neither the cpu nor the rx shift regi ster has accessed the rx fifo within 4 character times of the last byte. the timeout interrupt is cleared or reset when the cpu reads the rx fifo or another character enters it. these fifo related featur es allow optimization of cpu/uart transactions and are especially useful given the higher baud rate capability (256 kbaud). ring wake filter an optional filter is provided to prevent glitches to the wakeup circuitry and prevent unnecessary wakeup of the system when a phone is picked up or hung up. if enabled, this filter will be placed into the soft power management, smi and pme/sci wakeup event pat h of either of the uart ring indicator pins (nri1, nri2), or the nring pin, which is an alternate function on gp11 and gp62. this feature is enabled onto the nring pin or one of the ring indicator pins (nri1, nri2) via the ring filter select register defined below. if downloaded from: http:///
84 enabled, a frequency detection filter is placed in the path to the soft pow er management block, smi and pme interface t hat generates an active low pulse for the durat ion of a signal that produces 3 edges in a 200msec time period i.e., detects a pulse train of frequency 15hz or higher. this filter circuit runs off of the 32 khz clock. this circuit is powered by the vtr power supply. when this circuit is disabled, it will draw no current. the nring function is part of the soft power management block as an additional wakeup event, and the smi and pme interface logic. 1. a status and enable bit is in the soft power status and enable registers as follows: ? ring status bit - r/w: ring_sts, bit 3 of soft power status register 2 (logical device 8, 0xb3); latched, cleared on read. 1= ring indicator input occurred on the nring pin and, if enabled, caused the wakeup (activated npoweron). 0= nring input did not occur. ? ring enable bit - r/w: ring_en, bit 3 of soft power enable register 2 (logical device 8, 0xb1). 1=enable ring indication on nring pin as wakeup function to activate npoweron. 0=disable. 2. an enable bit is in the smi enable register 1 as follows: ? ring enable bit - r/w: ring_en, bit 0 of smi register 1 (system i/o space, at +14h). 1=enable ring indication on nring pin as smi function. 0=disable. note: the pme status bit for ring is used as the smi status bit for ring (see pme status register). 3. a status and enable bit is in the pme status and enable registers as follows: ? ring status bit - r/w: ring_sts, bit 5 of pme status register 1 (system i/o space, at +ch); latched, cleared by writing a 1 to this bit. 1= ring indicator input occurred on the nring pin and, if enabled, caused the npme/sci or smi. 0= nring input did not occur. ? ring enable bit - r/w: ring_en, bit 5 of pme enable register 1 (system i/o space, at +eh). 1=enable ring indication on nring pin as pme wakeup function. 0=disable. refer to logical device 8, 0xc6 for programming information the ring wakeup filter will produce an active low pulse for the period of time that nring, nri1 and/or nri2 is toggling. see figure below. downloaded from: http:///
85 figure 3 - ring wakeup filter output infrared interface the infrared interface provides a two-way wireless communications port using infrared as a transmission medium. several ir implementations have been provided for the second uart in this chip (logical device 5), irda 1.0 and amplitude shift keyed ir. the ir transmission can use the standard uart2 txd2 and rxd2 pins or optional irtx and irrx pins. these can be selected through the configur ation registers. irda 1.0 allows serial communication at baud rates up to 115.2 kbps. each word is sent serially beginning with a zero value start bit. a zero is signaled by sending a single ir pulse at the beginning of the serial bit time. a one is signaled by sending no ir pulse during the bit time. please refer to the ac timing fo r the parameters of these pulses and the irda waveform. the amplitude shift keyed ir allows asynchronous serial communication at baud rates up to 19.2k baud. each word is sent serially beginning with a zero value start bit. a zero is signaled by sending a 500khz waveform for the duration of the serial bit time. a one is signaled by sending no transmission during the bit time. please refer to the ac timing for the parameters of the ask-ir waveform. if the half-duplex option is chosen, there is a time- out when the direction of the transmission is changed. this time-out starts at the last bit transferred during a transmission and blocks the receiver input until the timeout expires. if the transmit buffer is loaded with more data before the time-out expires, the time r is restarted after the new byte is transmitted. if data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-out expires after the last receive bit has been received. if the start bit of another character is received during this time-out, the timer is restarted after the new character is received. the ir half- duplex time-out is programmable via crf2 in logical device 5. this register allows the time-out to be programmed to any value between 0 and 10msec in 100usec increments. nr in g r ing w akeup f ilter o utput downloaded from: http:///
86 parallel port this chip incorporates an ibm xt/at compatible parallel port. this supports the optional ps/2 type bi-directional parallel port (spp), the enhanced parallel port (epp) and the extended capabilities port (ecp) parallel port modes. refer to the configuration registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation. this chip also provides a mode for support of the floppy disk controller on the parallel port. the parallel port also incorporates smsc's chiprotect circuitry, which prevents possible damage to the parallel port due to printer power-up. the functionality of the pa rallel port is achieved through the use of eight addressable ports, with their associated register s and control gating. the control and data port are read/write by the cpu, the status port is read/wr ite in the epp mode. the address map of the parallel port is shown below: data port base address + 00h status port base address + 01h control port base address + 02h epp addr port base address + 03h epp data port 0 base address + 04h epp data port 1 base address + 05h epp data port 2 base address + 06h epp data port 3 base address + 07h the bit map of these registers is: d0 d1 d2 d3 d4 d5 d6 d7 note data port pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 1 status port tmout 0 0 nerr slct pe nack nbusy 1 control port strobe autofd ninit slc irqe pcd 0 0 1 epp addr port pd0 pd1 pd2 pd3 pd4 pd5 pd6 ad7 2,3 epp data port 0 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2,3 epp data port 1 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2,3 epp data port 2 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2,3 epp data port 3 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2,3 note 1: these registers are available in all modes. note 2: these registers are only available in epp mode. note 3: for epp mode, iochrdy must be connected to the isa bus. downloaded from: http:///
87 table 38 - parallel port connector host connector pin number standard epp ecp 1 111 nstrobe nwrite nstrobe 2-9 96-103 pdata<0:7> pd ata<0:7> pdata<0:7> 10 108 nack intr nack 11 107 busy nwait busy, periphack(3) 12 106 pe (nu) perror, nackreverse(3) 13 105 select (nu) select 14 110 nautofd ndat astb nautofd, hostack(3) 15 109 nerror (nu) nfault(1) nperiphrequest(3) 16 94 ninit (nu) ninit(1) nreverserqst(3) 17 95 nselectin naddrstrb nselectin(1,3) (1) = compatible mode (3) = high speed mode note: for the cable interconnection required for ecp support and the slave connector pin numbers, refer to the ieee 1284 extended capabilit ies port protocol and isa standard , rev. 1.14, july 14, 1993. this document is available from microsoft. downloaded from: http:///
88 ibm xt/at compatible, bi-directional and epp modes data port address offset = 00h the data port is located at an offset of '00h' from the base address. the data register is cleared at initialization by reset. during a write operation, the data regist er latches the contents of the data bus with t he rising edge of the niow input. the contents of th is register are buffered (non inverting) and output onto the pd0 - pd7 ports. during a read operation in spp mode, pd0 - pd7 ports are buffered (not latched) and output to the host cpu. status port address offset = 01h the status port is locat ed at an offset of '01h' from the base address. the contents of this register are latched for the duration of an nior read cycle. the bits of the status port are defined as follows: bit 0 tmout - time out this bit is valid in epp mode only and indicates that a 10 usec time out has occurred on the epp bus. a logic o means that no time out error has occurred; a logic 1 means t hat a time out error has been detected. this bit is cleared by a reset. writing a one to this bit cl ears the time out status bit. on a write, this bit is self clearing and does not require a write of a zero. writing a zero to this bit has no effect. bits 1, 2 - are not implemented as register bits, during a read of the printe r status register these bits are a low level. bit 3 nerr - nerror the level on the nerror input is read by the cpu as bit 3 of the printer status register. a logic 0 means an error has been detected; a logic 1 means no error has been detected. bit 4 slct - printer selected status the level on the slct input is read by the cpu as bit 4 of the printer status register. a logic 1 means the printer is on line; a logic 0 means it is not selected. bit 5 pe - paper end the level on the pe input is read by the cpu as bit 5 of the printer status register. a logic 1 indicates a paper end; a logic 0 indicates the presence of paper. bit 6 nack - nacknowledge the level on the nack input is read by the cpu as bit 6 of the printer status register. a logic 0 means that the printer has received a character and can now accept another. a logic 1 means that it is still processing the la st character or has not received the data. bit 7 nbusy - nbusy the complement of the le vel on the busy input is read by the cpu as bit 7 of the printer status register. a logic 0 in this bit means that the printer is busy and cannot a ccept a new character. a logic 1 means that it is ready to accept the next character. control port address offset = 02h the control port is locat ed at an offset of '02h' from the base address. the control register is initialized by the reset input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. bit 0 strobe - strobe this bit is inverted and output onto the nstrobe output. bit 1 autofd - autofeed this bit is inverted and output onto the nautofd output. a logic 1 causes the printer to generate a line feed after each line is printed. a logic 0 means no autofeed. downloaded from: http:///
89 bit 2 ninit - ninitiate output this bit is output onto the ninit output without inversion. bit 3 slctin - printer select input this bit is inverted and output onto the nslctin output. a logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. bit 4 irqe - interrupt request enable the interrupt request enable bit when set to a high level may be used to enable interrupt requests from the parallel port to the cpu. an interrupt request is generated on the ir q port by a positive going nack input. when the irqe bit is programmed low the irq is disabled. bit 5 pcd - parallel control direction parallel control direction is not valid in printer mode. in printer mode, t he direction is always out regardless of the state of th is bit. in bi-directional, epp or ecp mode, a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). bits 6 and 7 during a read are a low level, and cannot be written. epp address port address offset = 03h the epp address port is lo cated at an offset of '03h' from the base address. the address register is cleared at initialization by reset. during a write operation, the contents of db0- db7 are buffered (non inve rting) and output onto the pd0 - pd7 ports, the leading edge of niow causes an epp address write cycle to be performed, the trailing edge of iow latches the data for the duration of the epp write cycle. during a read operation, pd0 - pd7 ports are read, the leading edge of ior causes an epp address read cycle to be performed and the data output to the host cp u, the deassertion of addrstb latches the pdat a for the duration of the ior cycle. this register is only available in epp mode. epp data port 0 address offset = 04h the epp data port 0 is located at an offset of '04h' from the base address. the data register is cleared at initialization by reset. during a write operation, the c ontents of db0-db7 are buffered (non inverting) and output onto the pd0 - pd7 ports, the leading edge of niow causes an epp data write cycle to be performed, the trailing edge of iow latches the data for the duration of the epp write cycle. during a read operation, pd0 - pd7 ports are read, the leading edge of ior causes an epp read cycle to be performed and the data output to the host cpu, the deassertion of datastb latches the pdata for the duration of the ior cycle. this register is only available in epp mode. epp data port 1 address offset = 05h the epp data port 1 is located at an offset of '05h' from the base address. refer to epp data port 0 for a description of operation. this register is only available in epp mode. epp data port 2 address offset = 06h the epp data port 2 is located at an offset of '06h' from the base address. refer to epp data port 0 for a description of operation. this register is only available in epp mode. epp data port 3 address offset = 07h the epp data port 3 is located at an offset of '07h' from the base address. refer to epp data port 0 for a description of operation. this register is only available in epp mode. epp 1.9 operation when the epp mode is selected in the configuration register , the standard and bi- directional modes are also available. if no epp read, write or address cycle is currently executing, then the pdx bus is in the standard or downloaded from: http:///
90 bi-directional mode, and all output signals (strobe, autofd, init) are as set by the spp control port and direction is controlled by pcd of the control port. in epp mode, the system timing is closely coupled to the epp timing. for this reason, a watchdog timer is required to prevent system lockup. the timer indicates if more than 10usec have elapsed from the start of the epp cycle (nior or niow asserted) to nwait being deasserted (after command). if a time-out occurs, the current epp cycle is aborted and the ti me-out condition is indicated in status bit 0. during an epp cycle, if strobe is active, it overrides the epp write signal forcing the pdx bus to always be in a write mode and the nwrite signal to always be asserted. software constraints before an epp cycle is executed, the software must ensure that the contro l register bit pcd is a logic "0" (ie a 04h or 05h should be written to the control port). if the user leaves pcd as a logic "1", and attempts to perform an epp write, the chip is unable to perform the write (because pcd is a logic "1") and will appear to perform an epp read on the parallel bus, no error is indicated. epp 1.9 write the timing for a write operation (address or data) is shown in timing diagram epp write data or address cycle. iochrdy is driven active low at the start of each epp write and is released when it has been determined that the write cycle can complete. the write cycle can complete under the following circumstances: 1. if the epp bus is not ready (nwait is active low) when ndatastb or naddrstb goes active then the write can complete when nwait goes inactive high. 2. if the epp bus is ready (nwait is inactive high) then the chip must wait for it to go active low before changing the state of ndatastb, nwrite or naddrstb. the write can complete once nwait is determined inactive. write sequence of operation 1. the host selects an epp register, places data on the sdata bus and drives niow active. 2. the chip drives iochrdy inactive (low). 3. if wait is not asserted, the chip must wait until wait is asserted. 4. the chip places address or data on pdata bus, clears pdir, and asserts nwrite. 5. chip asserts ndatastb or naddrstrb indicating that pdata bus contains valid information, and the write signal is valid. 6. peripheral deasserts nwait, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle. 7. a) the chip deasserts ndatastb or naddrstrb, this marks the beginning of the termination phase. if it has not already done so, the peripheral should latch the information byte now. b) the chip latches the data from the sdata bus for the pdata bus and asserts (releases) iochrdy allowing the host to complete the write cycle. 8. peripheral asserts nwait, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. 9. chip may modify nwrite and npdata in preparation for the next cycle. downloaded from: http:///
91 epp 1.9 read the timing for a read operation (data) is shown in timing diagram epp read data cycle. iochrdy is driven active low at the start of each epp read and is released when it has been determined that the read cycle can complete. the read cycle can complete under the following circumstances: 1 if the epp bus is not ready (nwait is active low) when ndatastb goes active then the read can complete when nwait goes inactive high. 2. if the epp bus is ready (nwait is inactive high) then the chip must wait for it to go active low before changing the state of write or before ndatastb goes active. the read can complete once nwait is determined inactive. read sequence of operation 1. the host selects an epp register and drives nior active. 2. the chip drives iochrdy inactive (low). 3. if wait is not asserted, the chip must wait until wait is asserted. 4. the chip tri-stat es the pdata bus and deasserts nwrite. 5. chip asserts ndatastb or naddrstrb indicating that pdata bus is tri-stated, pdir is set and the nwrite signal is valid. 6. peripheral drives pdata bus valid. 7. peripheral deasserts nwait, indicating that pdata is valid and the chip may begin the termination phase of the cycle. 8. a) the chip latches the data from the pdata bus for the sdata bus and deasserts ndatastb or naddrstrb. this marks the beginning of the termination phase. b) the chip drives the valid data onto the sdata bus and asserts (releases) iochrdy allowing the host to complete the read cycle. 9. peripheral tri-states the pdata bus and asserts nwait, indicating to the host that the pdata bus is tri-stated. 10. chip may modify nwrite, pdir and npdata in preparation for the next cycle. epp 1.7 operation when the epp 1.7 mode is selected in the configuration register , the standard and bi- directional modes are also available. if no epp read, write or address cycle is currently executing, then the pdx bus is in the standard or bi-directional mode, and all output signals (strobe, autofd, init) are as set by the spp control port and direction is controlled by pcd of the control port. in epp mode, the system timing is closely coupled to the epp timing. for this reason, a watchdog timer is required to prevent system lockup. the timer indicates if more than 10usec have elapsed from the start of the epp cycle (nior or niow asserted) to the end of the cycle nior or niow deasserted). if a time-out occurs, the current epp cycle is aborted and the time-out condition is indicated in status bit 0. software constraints before an epp cycle is executed, the software must ensure that the contro l register bits d0, d1 and d3 are set to zero. also, bit d5 (pcd) is a logic "0" for an epp write or a logic "1" for and epp read. epp 1.7 write the timing for a write operation (address or data) is shown in timing diagram epp 1.7 write data or address cycle. iochrdy is driven active low when nwait is active low during the epp cycle. this can be used to extend the cycle time. the write cycle can complete when nwait is inactive high. downloaded from: http:///
92 write sequence of operation 1. the host sets pdir bit in the control register to a logic "0". this asserts nwrite. 2. the host selects an epp register, places data on the sdata bus and drives niow active. 3. the chip places address or data on pdata bus. 4. chip asserts ndatastb or naddrstrb indicating that pdata bus contains valid information, and the write signal is valid. 5. if nwait is asserted, iochrdy is deasserted until the peripheral deasserts nwait or a time-out occurs. 6. when the host deasserts niow the chip deasserts ndatastb or naddrstrb and latches the data from the sdata bus for the pdata bus. 7. chip may modify nwrite, pdir and npdata in preparation of the next cycle. epp 1.7 read the timing for a read operation (data) is shown in timing diagram epp 1.7 read data cycle. iochrdy is driven active low when nwait is active low during the epp cycle. this can be used to extend the cycle time. the read cycle can complete when nwait is inactive high. read sequence of operation 1. the host sets pdir bit in the control register to a logic "1". this deasserts nwrite and tri- states the pdata bus. 2. the host selects an epp register and drives nior active. 3. chip asserts ndatastb or naddrstrb indicating that pdata bus is tri-stated, pdir is set and the nwrite signal is valid. 4. if nwait is asserted, iochrdy is deasserted until the peripheral deasserts nwait or a time-out occurs. 5. the peripheral drives pdata bus valid. 6. the peripheral deasserts nwait, indicating that pdata is valid and the chip may begin the termination phase of the cycle. 7. when the host deasserts nior the chip deasserts ndatastb or naddrstrb. 8. peripheral tri-st ates the pdata bus. 9. chip may modify nwrite, pdir and npdata in preparation of the next cycle. downloaded from: http:///
93 table 39 - epp pin descriptions epp signal epp name type epp description nwrite nwrite o this signal is active low. it denotes a write operation. pd<0:7> address/data i/o bi-directional epp byte wide address and data bus. intr interrupt i this signal is active high and positive edge triggered. (pass through with no inversion, same as spp). wait nwait i this signal is active low. it is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. it is driven active as an indication that the device is ready for the next transfer. datastb ndata strobe o this signal is active low. it is used to denote data read or write operation. reset nreset o this signal is active low. when driven active, the epp device is reset to its initial operational mode. addrstb naddress strobe o this signal is active low. it is used to denote address read or write operation. pe paper end i same as spp mode. slct printer selected status i same as spp mode. nerr error i same as spp mode. pdir parallel port direction o this output shows the direct ion of the data transfer on the parallel port bus. a low means an output/write condition and a high means an input/read condition. this signal is normally a low (output/write) unless pcd of the control register is set or if an epp read cycle is in progress. note 1: spp and epp can use 1 common register. note 2: nwrite is the only epp output that can be over-ridden by spp control port during an epp cycle. for correct epp read cycles, pcd is required to be a low. downloaded from: http:///
94 extended capabilities parallel port ecp provides a number of advantages, some of which are listed below. the individual features are explained in greater detail in the remainder of this section. ? high performance half-duplex forward and reverse channel ? interlocked handshake, for fast reliable transfer ? optional single byte rle compression for improved throughput (64:1) ? channel addressing for low-cost peripherals ? maintains link and data layer separation ? permits the use of active output drivers ? permits the use of adaptive signal timing ? peer-to-peer capability vocabulary the following terms are used in this document: assert: when a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state. forward: host to pe ripheral communication. reverse: peripheral to host communication pword: a port word; equal in size to the width of the isa interface. for this implementation, pword is always 8 bits. 1 a high level. 0 a low level. these terms may be considered synonymous: ? periphclk, nack ? hostack, nautofd ? periphack, busy ? nperiphrequest, nfault ? nreverserequest, ninit ? nackreverse, perror ? xflag, select ? ecpmode, nselectln ? hostclk, nstrobe reference document: ieee 1284 extended capabilities port protoc ol and isa interface standard , rev 1.14, july 14, 1993. this document is available from microsoft. the bit map of the extended parallel port registers is: d7 d6 d5 d4 d3 d2 d1 d0 note data pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ecpafifo addr/rle address or rle field 2 dsr nbusy nack perror select nfault 0 0 0 1 dcr 0 0 direction ackinten se lectin ninit autofd strobe 1 cfifo parallel port data fifo 2 ecpdfifo ecp data fifo 2 tfifo test fifo 2 cnfga 0 0 0 1 0 0 0 0 cnfgb compress intrvalue parallel port irq parallel port dma ecr mode nerrintren dmaen serviceintr full empty note 1: these registers are available in all modes. note 2: all fifos use one common 16 byte fifo. note 3: the ecp parallel port config reg b refl ects the irq and drq select ed by the configuration registers. isa implementation standard this specification de scribes the standard isa interface to the extended c apabilities port (ecp). downloaded from: http:///
96 all isa devices supporti ng ecp must meet the requirements contained in th is section or the port will not be supported by microsoft. for a description of the ecp protocol, please refer to the ieee 1284 extended capabilities port protocol and isa interface standard , rev. 1.14, july 14, 1993. this document is available from microsoft. description the port is software and hardware compatible with existing parallel ports so that it may be used as a standard lpt port if ecp is not required. the port is designed to be simple and requires a small number of gates to implement. it does not do any "protocol" negotiation, ra ther it provides an automatic high burst- bandwidth channel that supports dma for ecp in both the forward and reverse directions. small fifos are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. the size of the fifo is 16 bytes deep. the port supports an automatic hands hake for the standard parallel port to improve co mpatibility mode transfer speed. the port also supports run length encoded (rle) decompression (required) in hardware. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times the next byte is to be repeated. decompression simply intercepts the rle byte and repeats the following byte the specified number of times. hardware support for compression is optional. downloaded from: http:///
96 table 40 - ecp pin descriptions name type description nstrobe o during write operations nstrobe regi sters data or address into the slave on the asserting edge (handshakes with busy). pdata 7:0 i/o contains address or data or rle data. nack i indicates valid data driven by t he peripheral when asserted. this signal handshakes with nautofd in reverse. periphack (busy) i this signal deasserts to indi cate that the peripheral can accept data. this signal handshakes with nstrobe in the fo rward direction. in the reverse direction this signal indicates whether the data lines contain ecp command information or data. the peripheral uses this signal to flow control in the forward direction. it is an "interlo cked" handshake with nstrobe. periphack also provides command information in the reverse direction. perror (nackreverse) i used to acknowledge a change in the direction the transfer (asserted = forward). the peripheral drives this signal low to acknowledge nreverserequest. it is an "interlocked" handshake with nreverserequest. the host relies upon nackreverse to determine when it is permitted to drive the data bus. select i indicates printer on line. nautofd (hostack) o requests a byte of data from t he peripheral when asserted, handshaking with nack in the reverse direction. in the forward direction this signal indicates whether the data lines cont ain ecp address or data. the host drives this signal to flow control in t he reverse direction. it is an "interlocked" handshake with nack. hostack also prov ides command information in the forward phase. nfault (nperiphrequest) i generates an error interrupt when asserted. this signal provides a mechanism for peer-to-peer communication. this signal is valid only in the forward direction. during ecp mode the peripheral is permitted (but not required) to drive this pin low to re quest a reverse transfer. the request is merely a "hint" to the host; the host has ultimate control over the transfer direction. this signal would be typically used to generate an interrupt to the host cpu. ninit o sets the transfer direction (assert ed = reverse, deasserted = forward). this pin is driven low to place the chan nel in the reverse direction. the peripheral is only allowed to drive t he bi-directional data bus while in ecp mode and hostack is low and nselectin is high. nselectin o always deasserted in ecp mode. downloaded from: http:///
97 register definitions the register definitions are based on the standard ibm addresses for lpt. all of the standard printer ports are supported. t he additional registers attach to an upper bit decode of the standard lpt port definition to avoid co nflict with standard isa devices. the port is equivalent to a generic parallel port interface and may be operated in that mode. the port registers vary depending on the mode field in the ecr. the table below lists these dependencies. operation of the devices in modes other that those specified is undefined. table 41 - ecp register definitions name address (note 1) ecp modes function data +000h r/w 000-001 data register ecpafifo +000h r/w 011 ecp fifo (address) dsr +001h r/w all status register dcr +002h r/w all control register cfifo +400h r/w 010 parallel port data fifo ecpdfifo +400h r/w 011 ecp fifo (data) tfifo +400h r/w 110 test fifo cnfga +400h r 111 configuration register a cnfgb +401h r/w 111 configuration register b ecr +402h r/w all extended control register note 1: these addresses are added to the parallel port base address as selected by configuration register or jumpers. note 2: all addresses are qualified with aen. refer to the aen pin definition. table 42 - mode descriptions mode description* 000 spp mode 001 ps/2 parallel port mode 010 parallel port data fifo mode 011 ecp parallel port mode 100 epp mode (if this option is enabled in the configurat ion registers) 101 reserved 110 test mode 111 configuration mode *refer to ecr register description downloaded from: http:///
98 data and ecpafifo port address offset = 00h modes 000 and 001 (data port) the data port is located at an offset of '00h' from the base address. the data register is cleared at initialization by reset. during a write operation, the data regist er latches the contents of the data bus on the rising edge of the niow input. the contents of th is register are buffered (non inverting) and output onto the pd0 - pd7 ports. during a read operation, pd0 - pd7 ports are read and output to the host cpu. mode 011 (ecp fifo - address/rle) a data byte written to this address is placed in the fifo and tagged as an ecp address/rle. the hardware at the ecp port tr ansmits this byte to the peripheral automatically. the operation of this register is ony defined for the forward direction (direction is 0). refer to the ecp parallel port forward timing diagram, located in the timing diagrams section of this data sheet . device status register (dsr) address offset = 01h the status port is locat ed at an offset of '01h' from the base address. bits 0 - 2 are not implemented as register bi ts, during a read of the printer status register thes e bits are a low level. the bits of the status po rt are defined as follows: bit 3 nfault the level on the nfault input is read by the cpu as bit 3 of the device status register. bit 4 select the level on the select input is read by the cpu as bit 4 of the device status register. bit 5 perror the level on the perror input is read by the cpu as bit 5 of the device status register. printer status register. bit 6 nack the level on the nack input is read by the cpu as bit 6 of the device status register. bit 7 nbusy the complement of the le vel on the busy input is read by the cpu as bit 7 of the device status register. device control register (dcr) address offset = 02h the control register is lo cated at an offset of '02h' from the base address. the control register is initialized to zero by the reset input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. bit 0 strobe - strobe this bit is inverted and output onto the nstrobe output. bit 1 autofd - autofeed this bit is inverted and output onto the nautofd output. a logic 1 causes the printer to generate a line feed after each line is printed. a logic 0 means no autofeed. bit 2 ninit - ninitiate output this bit is output onto the ninit output without inversion. bit 3 selectin this bit is inverted and output onto the nslctin output. a logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. bit 4 ackinten - interrupt request enable the interrupt request enable bit when set to a high level may be used to enable interrupt requests from the parallel port to the cpu due to a low to high transition on the nack input. refer to the description of the interr upt under operation, interrupts. bit 5 direction if mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. in a ll other modes, direction is valid and a logic 0 means that the printer port is in output mode (write); a l ogic 1 means that the printer port is in input mode (read). bits 6 and 7 during a read are a low level, and cannot be written. cfifo (parallel port data fifo) address offset = 400h mode = 010 downloaded from: http:///
99 bytes written or dmaed from the system to this fifo are transmitted by a hardware handshake to the peripheral using t he standard parallel port protocol. transfers to the fifo are byte aligned. this mode is only defined for the forward direction. ecpdfifo (ecp data fifo) address offset = 400h mode = 011 bytes written or dmaed from the system to this fifo, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ecp parallel port protocol. transfers to the fifo are byte aligned. data bytes from the peripheral are read under automatic hardware handshak e from ecp into this fifo when the direction bit is 1. reads or dmas from the fifo will return bytes of ecp data to the system. tfifo (test fifo mode) address offset = 400h mode = 110 data bytes may be read, written or dmaed to or from the system to this fifo in any direction. data in the tfifo will not be transmitted to the to the parallel port lines us ing a hardware protocol handshake. however, data in the tfifo may be displayed on the parallel port data lines. the tfifo will not sta ll when overwritten or underrun. if an attempt is made to write data to a full tfifo, the new data is not accepted into the tfifo. if an attempt is made to read data from an empty tfifo, the last data byte is re-read again. the full and empty bits must always keep track of the correct fifo state. t he tfifo will transfer data at the maximum isa rate so that software may generate performance metrics. the fifo size and interrupt threshold can be determined by writing bytes to the fifo and checking the full and serviceintr bits. the writeintrthreshold can be determined by starting with a full tfifo, setting the direction bit to 0 and emptying it a byte at a time until serviceintr is set. this may generate a spurious interrupt, but will indicate that the threshold has been reached. the readintrthreshold can be determined by setting the direction bit to 1 and filling the empty tfifo a byte at a time until serviceintr is set. this may generate a spurious interrupt, but will indicate that the threshold has been reached. data bytes are always read from the head of tfifo regardless of the value of the direction bit. for example if 44h, 33h, 22h is written to the fifo, then reading the tfifo will return 44h, 33h, 22h in the same order as was written. cnfga (configuration register a) address offset = 400h mode = 111 this register is a read on ly register. when read, 10h is returned. this indi cates to the system that this is an 8-bit implementation. (pword = 1 byte) cnfgb (configuration register b) address offset = 401h mode = 111 bit 7 compress this bit is read only. during a read it is a low level. this means that this chip does not support hardware rle compression. it does support hardware de-compression! bit 6 intrvalue returns the value on the isa irq line to determine possible conflicts. bits [5:3] parallel po rt irq (read-only) refer to table 39b. bits [2:0] parallel port dma (read-only) refer to table 39c. ecr (extended control register) address offset = 402h mode = all this register controls the extended ecp parallel port functions. bits 7,6,5 these bits are read/writ e and select the mode. bit 4 nerrintren downloaded from: http:///
100 read/write (valid only in ecp mode) 1: disables the interr upt generated on the asserting edge of nfault. 0: enables an interrupt pulse on the high to low edge of nfault. note that an interrupt will be generated if nfault is a sserted (interrupting) and this bit is written from a 1 to a 0. this prevents interrupts from being lost in the time between the read of th e ecr and the write of the ecr. bit 3 dmaen read/write 1: enables dma (dma starts when serviceintr is 0). 0: disables dma unconditionally. bit 2 serviceintr read/write 1: disables dma and all of the service interrupts. 0: enables one of the following 3 cases of interrupts. once one of the 3 service interrupts has occurred serviceintr bit shall be set to a 1 by hardware. it must be reset to 0 to re-enable the interrupts. writing this bit to a 1 will not cause an interrupt. case dmaen=1: during dma (this bit is set to a 1 when terminal count is reached). case dmaen=0 direction=0: this bit shall be set to 1 whenever there are writeintrthreshold or more bytes free in the fifo. case dmaen=0 direction=1: this bit shall be set to 1 whenever there are readintrthreshold or more valid bytes to be read from the fifo. bit 1 full read only 1: the fifo cannot acc ept another byte or the fifo is completely full. 0: the fifo has at least 1 free byte. bit 0 empty read only 1: the fifo is completely empty. 0: the fifo contains at least 1 byte of data. downloaded from: http:///
101 table 43 - extended control register r/w mode 000: standard parallel port mode . in this mode the fifo is reset and common collector drivers are used on the control lines (nstrobe, nautofd, ninit and nselectin). setting the direction bit will not tri-state the output drivers in this mode. 001: ps/2 parallel port mode. same as above except that direction may be used to tri-state the data lines and reading the data r egister returns the value on the data lines and not the value in the data register. all drivers have active pull-ups (push-pull). 010: parallel port fifo mode. this is the same as 000 except that bytes are written or dmaed to the fifo. fifo data is automatically transmitted usi ng the standard parallel por t protocol. note that this mode is only useful when direction is 0. all drivers have active pull-ups (push-pull). 011: ecp parallel port mode. in the forward direction (direction is 0) bytes placed into the ecpdfifo and bytes written to the ecpafifo are placed in a single fifo and transmitted automatically to the peripheral using ecp protocol. in the reverse direction (direction is 1) bytes are moved from the ecp parallel port and packed into bytes in t he ecpdfifo. all drivers have active pull-ups (push-pull). 100: selects epp mode: in this mode, epp is sele cted if the epp supported option is selected in configuration register l3- crf0. all drivers have active pull-ups (push-pull). 101: reserved 110: test mode. in this mode the fifo may be written and read, but the data will not be transmitted on the parallel port. all drivers have active pull-ups (push-pull). 111: configuration mode. in this mode the confga, confgb regist ers are accessible at 0x400 and 0x401. all drivers have active pull-ups (push-pull). table 43b table 43c irq selected config reg b bits 5:3 dma selected config reg b bits 2:0 15 110 3 011 14 101 2 010 11 100 1 001 10 011 all others 000 9 010 7 001 5 111 all others 000 downloaded from: http:///
102 operation mode switching/software control software will execute p1284 negotiation and all operation prior to a data transfer phase under programmed i/o control (mode 000 or 001). hardware provides an automatic control line handshake, moving data between the fifo and the ecp port only in the data transfer phase (modes 011 or 010). setting the mode to 011 or 010 will cause the hardware to initiate data transfer. if the port is in mode 000 or 001 it may switch to any other mode. if the por t is not in mode 000 or 001 it can only be switched into mode 000 or 001. the direction can only be changed in mode 001. once in an extended forward mode the software should wait for the fifo to be empty before switching back to mode 000 or 001. in this case all control signals will be deasserted before the mode switch. in an ecp reverse mode the software waits for all the data to be read from the fifo before changing back to mode 000 or 001. since the automatic hardware ecp reverse handshake only cares about the state of the fifo it may have acquired extra data which will be discarded. it may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. in this case the port will deassert naut ofd independent of the state of the transfer. t he design shall not cause glitches on the handshake signals if the software meets the constraints above. ecp operation prior to ecp operation the host must negotiate on the parallel port to dete rmine if the peripheral supports the ecp protocol. this is a somewhat complex negotiation carried out under program control in mode 000. after negotiation, it is necessary to initialize some of the port bits. the following are required: ? set direction = 0, enabling the drivers. ? set strobe = 0, causing the nstrobe signal to default to the deasserted state. ? set autofd = 0, causing the nautofd signal to default to the deasserted state. ? set mode = 011 (ecp mode) ecp address/rle bytes or data bytes may be sent automatically by writing the ecpafifo or ecpdfifo respectively. note that all fifo data transfers are byte wide and byte aligned. address/rle transfers are byte-wide and only allowed in the forward direction. the host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting mode = 011. when direct ion is 1 the hardware shall handshake for each ecp read data byte and attempt to fill the fifo. bytes may then be read from the ecpdfifo as long as it is not empty. ecp transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000. termination from ecp mode termination from ecp mode is similar to the termination from nibble/byte modes. the host is permitted to terminate from ecp mode only in specific well-defined stat es. the termination can only be executed while the bus is in the forward direction. to terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction. downloaded from: http:///
103 command/data ecp mode supports two advanced features to improve the effectiveness of the protocol for some applications. the features are implemented by allowing the transfer of normal 8 bit data or 8 bit commands. when in the forward direction, normal data is transferred when hostack is high and an 8 bit command is transferred when hostack is low. the most significant bit of the command indicates whether it is a run-lengt h count (for compression) or a channel address. when in the reverse direction, normal data is transferred when periphack is high and an 8 bit command is transferred when periphack is low. the most significant bit of the command is always zero. reverse channel addresses are seldom used and may not be suppor ted in hardware. table 44 - forward channel commands (hostack low) reverse channel commands (peripack low) d7 d[6:0] 0 run-length count (0-127) (mode 0011 0x00 only) 1 channel address (0-127) data compression the ecp port supports run length encoded (rle) decompression in hardware and can transfer compressed data to a peripheral. run length encoded (rle) compression in hardware is not supported. to transfer compressed data in ecp mode, the compression count is written to the ecpafifo and the data byte is written to the ecpdfifo. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times the next byte is to be repeated. decompression simply intercepts the rle byte and repeats the following byte the specified number of ti mes. when a run-length count is received from a peripheral, the subsequent data byte is re plicated the specified number of times. a run- length count of zero specifies that only one byte of data is represented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. to prevent data expansion, however, run- length counts of zero should be avoided. pin definition the drivers for nstrobe, nautofd, ninit and nselectin are open-collector in mode 000 and are push-pull in all other modes. isa connections the interface can never stall causing the host to hang. the width of data tr ansfers is strictly controlled on an i/o address basis per this specification. all fifo-dma transfers are byte wide, byte aligned and end on a byte boundary. (the pword value can be obtained by reading configuration register a, cnfga, described in the next section). single byte wide transfers are always possible with standard or ps/2 mode using program control of the control signals. interrupts the interrupts are enabled by serviceintr in the ecr register. serviceintr = 1 disables the dma and all of the service interrupts. serviceintr = 0 enables the selected interrupt condition. if the interrupting condition is valid, then the interrupt is generated immediately when this bit is changed from a 1 to a 0. this can occur during programmed i/o if the number of bytes removed or added from/to the fifo does not cross the threshold. downloaded from: http:///
104 the interrupt generated is isa friendly in that it must pulse the interrupt line low, allowing for interrupt sharing. after a brief pulse low following the interrupt event, the inte rrupt line is tri-stated so that other interrupts may assert. an interrupt is generated when: 1. for dma transfers: when serviceintr is 0, dmaen is 1 and the dma tc is received. 2. for programmed i/o: a. when serviceintr is 0, dmaen is 0, direction is 0 and there are writeintrthreshold or more free bytes in the fifo. also, an interrupt is generated when serviceintr is cleared to 0 whenever there are writeintrthr eshold or more free bytes in the fifo. b.(1) when serviceintr is 0, dmaen is 0, direction is 1 and there are readintrthreshold or more bytes in the fifo. also, an interrupt is generated when serviceintr is cleared to 0 whenever there are readintrthreshold or more bytes in the fifo. 3. when nerrintren is 0 and nfault transitions from high to low or when nerrintren is set from 1 to 0 and nfault is asserted. 4. when ackinten is 1 and the nack signal transitions from a low to a high. fifo operation the fifo threshold is set in the chip configuration registers. all data transfer s to or from the parallel port can proceed in dma or programmed i/o (non-dma) mode as indicated by the selected mode. the fifo is used by selecting the parallel port fifo mode or ecp parallel port mode. (fifo test mode will be addressed separately.) after a reset, the fifo is disabled. each data byte is transferred by a programmed i/o cycle or pdrq depending on the selection of dma or programmed i/o mode. the following paragraphs de tail the operation of the fifo flow control. in these descriptions, ranges from 1 to 16. the parameter fifothr, which the user programs, is one less and ranges from 0 to 15. a low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. the host must be very responsive to the service request. this is the desired case for use with a "fast" system. a high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. dma transfers dma transfers are always to or from the ecpdfifo, tfifo or cfifo. dma ut ilizes the standard pc dma services. to use the dma transfers, the host first sets up the direction and state as in the programmed i/o case. then it programs the dma controller in the host with the desired count and memory address. lastly it sets dmaen to 1 and serviceintr to 0. the ecp requests dma transfers from the host by activating the pdrq pin. the dma will empty or fill the fifo using the appropriate direction and mode. when the terminal count in the dma controller is reached, an interrupt is generated and se rviceintr is asserted, disabling dma. in order to prevent possible blocking of refresh requests dreq shall not be asserted for more than 32 dma cycles in a row. the fifo is enabled directly by asserting npdack and addresses need not be valid. pintr is generated when a tc is received. pdrq must not be asserted for more than 32 dma cycles in a row. after the 32nd cycle, pdrq must be kept unasserted until npdack is deasserted for a minimum of 350nsec. (note: the only way to properly terminate dma transfers is with a tc.) dma may be disabled in the middle of a transfer by first disabling the host dma controller. then setting serviceintr to 1, followed by setting dmaen to 0, and waiting for the fifo to become empty or full. restarting the dma is accomplished by enabling dma in the host, setting dmaen to 1, followed by setting serviceintr to 0. downloaded from: http:///
105 dma mode - transfers from the fifo to the host (note: in the reverse m ode, the peripheral may not continue to fill the fifo if it runs out of data to transfer, even if the chip continues to request more data from the peripheral.) the ecp activates the pdrq pin whenever there is data in the fifo. the dma controller must respond to the request by reading data from the fifo. the ecp will deactivate the pdrq pin when the fifo becomes empty or when the tc becomes true (qualified by npdack), indicating that no more data is required. pdrq goes inactive after npdack goes active for the last byte of a data transfer (or on the active edge of nior, on the last byte, if no edge is present on npdack). if pdrq goes inactive due to the fifo going empty, then pdrq is active again as soon as there is one byte in the fifo. if pdrq goes inactive due to the tc, then pdrq is active again when there is one byte in the fifo, and serviceintr has been re-enabled. (note: a data underrun may occur if pdrq is not removed in time to prevent an unwanted cycle). programmed i/o mode or non-dma mode the ecp or parallel port fifos may also be operated using interrupt driven programmed i/o. software can determine the writeintrthreshold, readintrthreshold, and fifo depth by accessing the fifo in test mode. programmed i/o transfers are to the ecpdfifo at 400h and ecpafifo at 000h or from the ecpdfifo located at 400h, or to/from the tfifo at 400h. to use the programmed i/o transfers, the host first sets up the direction and state, sets dmaen to 0 and serviceintr to 0. the ecp requests programmed i/o transfers from the host by activating the pintr pin. the programmed i/o will empty or fill the fifo using the appropriate direction and mode. note: a threshold of 16 is equivalent to a threshold of 15. these two cases are treated the same. programmed i/o - transfers from the fifo to the host in the reverse direction an interrupt occurs when serviceintr is 0 and r eadintrthreshold bytes are available in the fifo. if at this time the fifo is full it can be emptied completely in a single burst, otherwise readintrthreshold bytes may be read from the fifo in a single burst. readintrthreshold =(16-) data bytes in fifo an interrupt is generated when serviceintr is 0 and the number of bytes in the fifo is greater than or equal to (16-). (if the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the fifo). the pint pin can be used for interrupt-driven systems. the host must respond to the request by reading data from the fifo. this process is repeated until the last byte is transferred out of the fifo. if at this time the fifo is full, it can be completely emptied in a single burst, otherwise a minimum of (16- ) bytes may be read from the fifo in a single burst. downloaded from: http:///
106 programmed i/o - transfers from the host to the fifo in the forward direction an interrupt occurs when serviceintr is 0 and there ar e writeintrthreshold or more bytes free in the fifo. at this time if the fifo is empty it can be f illed with a single burst before the empty bit needs to be re-read. otherwise it may be fille d with writeintrthreshold bytes. writeintrthreshold = ( 16-) free bytes in fifo an interrupt is generated when serviceintr is 0 and the number of bytes in the fifo is less than or equal to . (if the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the fifo.) the pint pin can be used for interrupt-driven systems. the host must respond to the request by writing data to the fifo. if at this time the fifo is empty, it can be completely filled in a single burst, otherwise a minimum of (16-) bytes may be written to the fifo in a single burst. this process is repeated until the last byte is transferred into the fifo. downloaded from: http:///
107 parallel port floppy disk controller the floppy disk control signals are available optionally on the parallel port pins. when this mode is selected, the paralle l port is not available. there are two modes of operation, ppfd1 and ppfd2. these modes can be selected in the parallel port mode register, as defined in the parallel port mode register, logical device 3, at 0xf1. ppfd1 has only drive 1 on the parallel port pins; ppfd2 has drive 0 and 1 on the parallel port pins. when the ppfdc is selected the following pins are set as follows: 1. npdack: high-z 2. pdrq: not ecp = high-z, ecp & dmaen = 0, ecp & not dmaen = high-z 3. pintr: not active, this is hi-z or low depending on settings. note: npdack, pdrq and pintr refer to the ndack, drq and irq chosen for the parallel port. the following parallel port pins are read as follows by a read of the parallel port register: 1. data register (read) = last data register (write) 2. control register read as "cable not connected" strobe, autofd and slc = 0 and ninit =1 3. status register read s: nbusy = 0, pe = 0, slct = 0, nack = 1, nerr = 1 the following fdc pins are all in the high impedence state when t he ppfdc is actually selected by the drive select register: 1. nwdata, densel, nhdsel, nwgate, ndir, nstep, nds1, nds0, nmtr0, nmtr1. 2. if ppfdx is selected, then the parallel port can not be used as a parallel port until "normal" mode is selected. the fdc signals are muxed onto the parallel port pins as shown in table 42. for acpi compliance the fdd pins that are multiplexed onto the pa rallel port function independently of the state of the parallel port controller. for exampl e, if the fdc is enabled onto the parallel port the multiplexed fdd interface functions norma lly regardless of the parallel port power control, cr22.3. table 41 illustrates this functionality. table 45 - parallel port fdd control parallel port power parallel port fdc control parallel port fdc state parallel port state cr22.3 ld3:crf1.1 ld3:crf1.0 1 0 0 off on 0 0 0 off off x 1 x on off x 1 (note 1 ) note 1 : the parallel port control register reads as cable not connected when the parallel port fdc is enabled; i.e., strobe = autofd = slc = 0 and ninit = 1. downloaded from: http:///
108 table 46 - fdc parallel port pins spp mode pin direction f dc mode pin direction nstrobe i/o (nds0) i/(o) note1 pd0 i/o nindex i pd1 i/o ntrk0 i pd2 i/o nwp i pd3 i/o nrdata i pd4 i/o ndskchg i pd5 i/o - - pd6 i/o (nmtr0) i/(o) note1 pd7 i/o - - nack i nds1 o busy i nmtr1 o pe i nwdata o slct i nwgate o nalf i/o drvden0 o nerror i nhdsel o ninit i/o ndir o nslctin i/o nstep o note 1: these pins are outputs in mode ppfd2, inputs in mode ppfd1. refer to force write protect in the floppy disk controller section for information on the floppy disk controller force write protect function. downloaded from: http:///
109 power management power management capabilities are provided for the following logical devices: floppy disk, uart 1, uart 2 and the parallel port. for each logical device, two types of power management are provided; direct powerdown and auto powerdown. fdc power management direct power management is controlled by cr22. refer to cr22 for more information. auto power management is enabled by cr23-b0. when set, this bit allows fdc to enter powerdown when all of the following conditions have been met: 1. the motor enable pins of register 3f2h are inactive (zero). 2. the part must be idle; msr=80h and int = 0 (int may be high even if msr = 80h due to polling interrupts). 3. the head unload timer must have expired. 4. the auto powerdown timer (10msec) must have timed out. an internal timer is init iated as soon as the auto powerdown command is enabled. the part is then powered down when all the conditions are met. disabling the auto power down mode cancels the timer and holds the fdc block out of auto powerdown. dsr from powerdown if dsr powerdown is used when the part is in auto powerdown, the dsr power down will override the auto powerdown. however, when the part is awakened from dsr powerdown, the auto powerdown will once agai n become effective. wake up from auto powerdown if the part enters the powerdown state through the auto powerdown mode, then the part can be awakened by reset or by appropriate access to certain registers. if a hardware or software reset is used then the part will go through the normal reset sequence. if the access is through the selected registers, then the fdc resumes operation as though it was never in powerdown. besides activating the reset pin or one of the software reset bits in the dor or dsr, the following register accesses will wake up the part: 1. enabling any one of the motor enable bits in the dor register (r eading the dor does not awaken the part). 2. a read from the msr register. 3. a read or write to the data register. once awake, the fdc will reinitiate the auto powerdown timer for 10 ms. the part will powerdown again when all the powerdown conditions are satisfied. register behavior table 44 illustrates the at and ps/2 (including model 30) configuration re gisters available and the type of access permitted. in order to maintain software transparency, access to all the registers must be maintained. as table 44 shows, two sets of registers are disti nguished based on whether their access results in the part remaining in powerdown state or exiting it. downloaded from: http:///
110 access to all other registers is possible without awakening the part. these registers can be accessed during powerdown without changing the status of the part. a read from these registers will reflect the true status as shown in the register description in the fdc description. a write to the part will result in the part retaining the data and subsequently reflecting it when the part awakens. accessing the part during powerdown may cause an increase in the power consumption by the part. the part will revert back to its low power mode when the access has been completed. pin behavior this chip is specifically designed for systems in which power conservation is a primary concern. this makes the behavior of the pins during powerdown very important. the pins can be divided into two major categories: system interface and floppy disk drive interface. the floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied to the pin within the part's power supply range. most of the system interface pins are left active to monitor system accesses that may wake up the part. system interface pins table 45 gives the state of the system interface pins in the powerdown stat e. pins unaffected by the powerdown are labeled "unchanged". input pins are "disabled" to pr event them from causing currents internal to the chip when they have indeterminate input values. downloaded from: http:///
111 table 47 - pc/at and ps/2 available registers available registers base + address pc-at ps/2 (model 30) access permitted access to these registers does not wake up the part 00h ---- sra r 01h ---- srb r 02h dor (1) dor (1) r/w 03h --- --- --- 04h dsr (1) dsr (1) w 06h --- --- --- 07h dir dir r 07h ccr ccr w access to these registers wakes up the part 04h msr msr r 05h data data r/w note 1: writing to the dor or dsr does not wake up the part, however, writing any of the motor enable bits or doing a software reset (via dor or dsr reset bits) will wake up the part. table 48 - state of system pins in auto powerdown system pins state in auto powerdown input pins nior unchanged niow unchanged sa[0:9] unchanged sd[0:7] unchanged reset_drv unchanged dackx unchanged tc unchanged output pins irqx unchanged (low) sd[0:7] unchanged drqx unchanged (low) fdd interface pins all pins in the fdd interface which can be connected directly to the fl oppy disk drive itself are either disabled or tristated. pins used for local logic control or part programming are unaffected. table 46 depicts the state of the floppy disk driv e interface pins in the powerdown state. downloaded from: http:///
112 table 49 - state of floppy disk drive interface pins in powerdown fdd pins state in auto powerdown input pins nrdata input nwprot input ntr0 input nindex input ndskchg input output pins nmtr0 tristated nds0 tristated ndir active nstep active nwdata tristated nwgate tristated nhdsel active drvden[0:1] active downloaded from: http:///
113 uart power management direct power management is controlled by cr22. refer to cr22 for more information. auto power management is enabled by cr23-b4 and b5. when set, these bits allow the following auto power management operations: 1. the transmitter enters auto powerdown when the transmit buffer and shift register are empty. 2. the receiver enters powerdown when the following conditions are all met: a. receive fifo is empty b. the receiver is waiting for a start bit. note: while in powerdown the ring indicator interrupt is still valid and transitions when the ri input changes. exit auto powerdown the transmitter exits powerdown on a write to the xmit buffer. the receiver exits auto powerdown when rxdx changes state. parallel port direct power management is controlled by cr22. refer to cr22 for more information. auto power management is enabled by cr23-b3. when set, this bit allows the ecp or epp logical parallel port blocks to be placed into powerdown when not being used. the epp logic is in powerdown under any of the following conditions: 1. epp is not enabled in the configuration registers. 2. epp is not selected through ecr while in ecp mode. the ecp logic is in powerdown under any of the following conditions: 1. ecp is not enabled in the configuration registers. 2 spp, ps/2 parallel port or epp mode is selected through ecr while in ecp mode. exit auto powerdown the parallel port logic can change powerdown modes when the ecp mode is changed through the ecr register or when the parallel port mode is changed through the confi guration registers. v bat support this chip requires a (tbd) microamp battery supply (v bat ) to provide battery backed up registers. these register s retain the contents of the general purpose regist ers and wake-up event registers. v tr support the fdc37b72x requires a 25 ma trickle (standby) supply (v tr ) to provide sleep current for the programmable wake-up events in the soft power management logic, sci, pme and smi interfaces when v cc is removed. if the fdc37b72x is not intended to provide wake-up capabilities on standby power, v tr can be connected to v cc . v tr powers the ir interface, the pme registers, the pm e interface, the acpi registers, the sci interf ace, the gpio logic, the gpio configuration regi sters and other wakeup related configuration registers. the v tr pin generates a v tr power-on-reset signal to initialize certain component s. all wakeup event registers and related logic are battery backed-up to retain the configurat ion of the wakeup events upon a power loss (i.e., v cc = 0 v and v tr = 0 v). these registers are reset on a v bat por. the following section lists t he pins that are active under vtr power. internal pwrgood an internal pwrgood logical control is included to minimize the effects of pin-state uncertainty in the host interface as v cc cycles on and off. when the internal pwrgood signal is 1 downloaded from: http:///
114 (active), v cc is > 4v, and the fdc37b72x host interface is active. when the internal pwrgood signal is 0 (inactive), v cc is 4v, and the fdc37b72x host interface is inactive; that is, isa bus reads and writes will not be decoded. the fdc37b72x device pins kdat, mdat, irrx, nri1, nri2, rxd1, rxd2, nring, button_in and the gpios are part of the pme interface and remain active as inputs for wakeup when the internal pwrgood signal has gone inactive, provided v tr is powered. in addition, the npme/sci, gp53/irq11 (sci pin), npoweron and clk32out pins remain active as outputs when the internal pwrgood is inactive and v tr is powered. the internal pwrgood signal is also used to disable the ir half duplex timeout. note: if v tr is to be used for programmable wake-up events when v cc is removed, v tr must be at its full minimum potential at least 10 s before v cc begins a power-on cycle. when v tr and v cc are fully powered, t he potential difference between the two supplies must not exceed 500mv. 32.768 khz standby clock output the fdc37b72x provides a 32.768 khz trickle clock output pin. this out put is active as long as v tr is present. oscillator crystal oscillator input. a 32.768khz crystal connected externally on the xtal1 and xtal2 pins generates the 32. 768khz input clock. maximum clock frequency is 32.768khz. this oscillator is also used as an internal clock source for functions within the fdc37b72x. there is a bit in the ring f ilter select register that can be used to select t he load capacitance of the crystal to ensure accurate time keeping. this bit is defined as follows: bit 6 - xtal_cap. this bit is used to specify the 32khz xtal load capacitance (12pf vs. 6pf): 0=12pf (default), 1=6pf. downloaded from: http:///
115 serial irq the fdc37b72x supports serial interrupts to transmit in terrupt information to the host system. the serial interrupt scheme adheres to the serial irq s pecification for pci systems, version 6.0. timing diagrams for irqser cycle pciclk = 33mhz_in pin irqser = sirq pin a) start frame timing with source sampled a low pulse on irq1 rt s rt s irqser pciclk host controller irq1 irq1 drive source rt none irq0 frame irq1 frame s rt irq2 frame none start start frame h sl orh 1 h=host control r=recovery sl=slave control t=turn-around s=sample 1) start frame pulse can be 4-8 clocks wide. downloaded from: http:///
116 b) stop frame timing with host using 17 irqser sampling period s rt s irqser pciclk host controller irq15 driver rt none irq14 irq15 s rt iochck# none stop rt stop frame h i start next cycle 1 2 3 frame frame frame h=host control t=turn-around r=recovery s=sample i= idle. 1) stop pulse is 2 clocks wide for quiet mode, 3 clocks wide for continuous mode. 2) there may be none, one or more idle states during the stop frame. 3) the next irqser cycles start frame pulse may or may not start immediately after the turn-around clock of the stop frame. irqser cycle control there are two modes of operation for the irqser start frame. 1) quiet (active) mode : any device may initiate a start frame by driving the irqser low for one clock, while the irqser is idle. after driving low for one clock the irqser must immediately be tri-stated without at any ti me driving high. a start frame may not be initiat ed while the irqser is active. the irqser is idle between stop and start frames. the irqser is active between start and stop frames. th is mode of operation allows the irqser to be idle when there are no irq/data transitions whic h should be most of the time. once a start frame has been initiated the host controller will take over driving the irqser low in the next clock and will continue driving the irqser low for a programmable period of three to seven clocks. this makes a total low pulse width of four to eight clocks. finally, the host controller will drive the irqser back high for one cl ock, then tri-state. any irqser device (i.e., the fdc37b72x) which detects any transition on an irq/data line for which it is responsible must initiate a start frame in order to updat e the host controller unless the irqser is already in an irqser cycle and the irq/data transition can be delivered in that irqser cycle. 2) continuous (idle) mode : only the host controller can initiate a start frame to update irq/data line information. all other irqser agents become passive and may not initiate a start frame. irqser will be driven low for four to eight clocks by host controller. this mode has two functions. it can be used to stop or idle the irqser or the host controller can operate irqser in a continuous mode by initiating a start frame at the end of every stop frame. an irqser mode transition can only occur during the stop frame. upon reset, irqser bus is defaulted to continuous mode, downloaded from: http:///
117 therefore only the host controller can initiate the first start frame. slaves must continuously sample the stop frames pulse width to determine the next irqser cycles mode. irqser data frame once a start frame has been initiated, the fdc37b72x will watch for the rising edge of the start pulse and start counting irq/data frames from there. each irq/data frame is three clocks: sample phase, recovery phase, and turn-around phase. during the sample phase the fdc37b72x must drive the irqser (sirq pin) low, if and only if, its last detected irq/data value was low. if its detected irq/data value is high, irqser must be left tri-stated. during the recovery phase the fdc37b72x must drive the serirq high, if and only if, it had driven the irqser low during the previous sample phase. during the turn-around phase the fdc37b72x must tri-state the serirq. the fdc37b72x will drive the irqser line low at the appropriate sample point if its associated irq/data line is low, regardless of which device initiated the start frame. the sample phase for each irq/data follows the low to high transition of the start frame pulse by a number of clocks equal to the irq/data frame times three, minus one. (e.g. the irq5 sample clock is the sixth irq/data frame, (6 x 3) - 1 = 17th clock after the rising edge of the start pulse). irqser sampling periods irqser period signal sampled # of clocks past start 1 not used 2 2 irq1 5 3 nsmi/irq2 8 4 irq3 11 5 irq4 14 6 irq5 17 7 irq6 20 8 irq7 23 9 irq8 26 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 irq13 41 15 irq14 44 16 irq15 47 downloaded from: http:///
118 the sirq data frame will now support irq2 from a logical device, previously irqser period 3 was reserved for use by the system management interrupt (nsmi). when using period 3 for irq2 the user should mask off the smi via the smi enable register. likewise, when using period 3 for nsmi the user should not configure any logical devices as using irq2. irqser period 14 is used to transfer irq13. logical devices 0 (fdc), 3 (par port), 4 (ser port 1), 5 (ser port 2), and 7 (kbd) shall have irq13 as a choice for their primary interrupt. the smi is enabled onto t he smi frame of the serial irq via bit 6 of smi enable register 2 and onto the smi pin via bit 7 of the smi enable register 2. note: when serial irqs are used, nirq8, nsci and nsmi may be output on one of their respective pin options. see the irq mux configuration register. stop cycle control once all irq/data frames have completed the host controller will terminate irqser activity by initiating a stop frame. only the host controller can initiate the stop fr ame. a stop frame is indicated when the irqser is low for two or three clocks. if the stop frames low time is two clocks then the next irqser cycles sampled mode is the quiet mode; and any irqser device may initiate a start frame in the second clock or more after the rising edge of the stop frames pulse. if the stop frames low time is three clocks then the next irqser cycles sampled mode is the continuos mode; and only the host controller may initiate a start frame in the second clock or more after the rising edge of the stop frames pulse. latency latency for irq/data updates over the irqser bus in bridge-less systems with the minimum irq/data frames of se venteen, will range up to 96 clocks (3.84 s with a 25mhz pci bus or 2.88us with a 33mhz pci bus). if one or more pci to pci bridge is added to a system, the latency for irq/data updat es from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses. eoi/isr read latency any serialized irq scheme has a potential implementation issue related to irq latency. irq latency could cause an eoi or isr read to precede an irq transition that it should have followed. this could cause a system fault. the host interrupt controller is responsible for ensuring that thes e latency issues are mitigated. the recommended solution is to delay eois and isr reads to the interrupt controller by the same amount as the irqser cycl e latency in order to ensure that these event s do not occur out of order. ac/dc specification issue all irqser agents must drive / sample irqser synchronously related to the rising edge of pci bus clock. irqser (sirq) pin uses the electrical specification of pci bus. electrical parameters will follow pci spec. section 4, sustained tri-state. reset and initialization the irqser bus uses reset_drv as its reset signal. the irqser pin is tri-stated by all agents while reset_drv is active. with reset, irqser slaves are put into the (continuous) idle mode. the host controller is responsible for starting the initial irqser cycle to collect systems irq/data default values. the system then follows with the continuous/quiet mode protocol (stop frame pulse width) for subsequent irqser cycles. it is host downloaded from: http:///
119 controllers responsibility to provide the default values to 8259s and other system logic before the first irqser cycle is performed. for irqser system suspend, insertion, or removal application, the host controller should be programmed into continuous (idle) mode first. this is to guarantee irqser bus is in idle state before the system c onfiguration changes. downloaded from: http:///
120 bios buffer the chip contains one 245 type buffer that can be used for a bios buffer. if the bios buffer is not used, then nromcs must be tied high or pulled up to vcc with a resistor so as not to interfere with the boot rom. this function allows data transmission from the rd bus to the sd bus or from the sd bus to the rd bus. the direction of the transfer is controlled by nromoe. the enable input, nromcs, can be used to disable the transfer and isolate the buses. nromcs nromoe description l l rd[0:7] data to sd[0:7] bus l h sd[0:7] data to rd[0:7] h x isolation rd bus functionality the following cases described below illustrate the use of the rd bus. case 1: nromcs and nromoe as original function. the rd bus c an be used as the rd bus or one or more rd pins can be programmed as alternate function. th ese alternate functions behave as follows: if in rd to sd mode, any value on rdx will appear on sdx; if in sd to rd mode, sdx will not appear on rdx, rdx gets the alternate function value. note: in this case, nromcs=0, nromoe=1. case 2: nromoe as gpio function. (nromoe internally tied to ground). in this case, the rd bus is a unidirectional bus (read only) controlled by nromcs. if nromcs = 0, the values on rd0-7 appear on sd0-7. if nromcs = 1, the rd bus is disabled, and nothing appears on the sd bus. note: any rd bus pin can be programmed as an alternate function, however, if nromcs=0, then anything on the rd bus will appear on the sd bus. case 3: nromcs as gpio function. (nromcs internally tied to vdd.) the rd bus floats - cannot use as a bus. any pin can be programmed as an alternate function. case 4: nromcs and nromoe as gpio function. same as case 3. case 5 : parallel irq enabled; rd bus pins, nromoe, nromcs are used as irq pins. downloaded from: http:///
121 general purpose i/o the fdc37b72x provides a set of flexible input/output control func tions to the system designer through the 20 dedicated independently programmable general purpose i/o pins (gpio). the gpio pins can perform simple i/o or can be individually configured to provide predefined alternate functions. vbat power-on-reset configures all gpio pins as non-inverting inputs. description each gpio port requires a 1-bit data register and an 8-bit configuration cont rol register. the data register for each gpio port is represented as a bit in one of three 8-bit gpio data registers, gp1, gp5, and gp6. all of the gpio registers are located in logical device block no. 8 in the fdc37b72x device confi guration space. the gpio data registers are also optionally available at different addresses when the fdc37b72x is in the run state (see the run state gpio register access section below). the gpio ports with their alternate functions and configuration state regist er addresses are listed in table 50. note: four bits 1, 5-7 of gp5 are not implemented. table 50 - general purpose i/o port assignments pin no. qfp default function alt. func. 1 alt. func. 2 alt. func. 3 data register 5 (hex) data register bit no. config. register 5 (hex) 77 gpio nsmi - - gp1 0 cre0 78 gpio nring eeti 1 - (crf6) 1 cre1 79 gpio wdt p17/p12 4 eeti 1 2 cre2 80 gpio led - - 3 cre3 81 gpio irrx2 - - 4 cre4 82 gpio irtx2 - - 5 cre5 4 gpio nmtr1 - - 6 cre6 6 gpio nds1 - - 7 cre7 39 pci_clk irq14 gpio - gp5 0 crc8 2 gpio drvden1 irq8 nsmi (crf9) 2 crca 91 nromcs 2 irq11 gpio eeti 1 3 crcb 92 nromoe 2 irq12 gpio eeti 1 4 crcc 83 rd0 2,3 irq1 gpio nsmi gp6 0 crd0 84 rd1 2,3 irq3 gpio led (crfa) 1 crd1 85 rd2 2,3 irq4 gpio nring 2 crd2 86 rd3 2,3 irq5 gpio wdt 3 crd3 87 rd4 2,3 irq6 gpio p17/p12 4 4 crd4 88 rd5 2,3 irq7 gpio - 5 crd5 89 rd6 2,3 irq8 gpio - 6 crd6 90 rd7 2,3 irq10 gpio - 7 crd7 note 1: refer to the section on ei ther edge triggered interrupt inputs. note 2: at power-up, rd0-7, nromcs and nromoe function as the xd bus. to use rd0-7 for alternate functions, nromcs must stay high until those pins are fi nished being programmed. note 3: these pins cannot be programmed as open drain pins in their original function. note 4: the function of p17 or p1 2 is selected via the p17/p12 select bit in the ring filter select register in logical device 8 at 0xc6. note 5: the gpio data and configuration register s are located in logical device block number 8. downloaded from: http:///
122 run state gpio data register access the gpio data registers as well as the watchdog timer control, and the soft power enable and status registers can be accessed by the host when the chip is in the run state if cr03 bit[7] = 1. the host uses an index and data port to access these registers (table 51). the index and data port power-on default addresses are 0xea and 0xeb respectively. in t he configuratio n state the index port address may be re-programmed to 0xe0, 0xe2, 0xe4 or 0x ea; the data port address is automatically set to the index port address + 1. upon exiting the configurat ion state the new index and data port addresses are used to access the gpio data, soft power status and enable, and the watchdog timer control registers. for example, to access the gp1 data register when in the run state, t he host should perform an i/o write of 0x01 to the index port address (0xex) to select gp1 and then read or write the data port (at index+1) to access the gp1 register. generally, to access any gpio data register gpx the host should perform an i/o write of 0x0x to the index port address and then access gpx through the data port. the soft power and watchdog timer control registers are accessed similarly. table 51 - index and data ports port name port address run state access index 0xe0, e2, e4, ea 0x01-0x0f data index address + 1 access to gp1, watchdog timer control, gp5, gp6, and the soft power status and enable registers (see table 52). table 52 - run state accessable configuration registers run state register address (index) register (configuration state addressing 1 ) 0x01 gp1 (l8 - crf6) 0x03 watchdog timer control (l8 - crf4) 0x05 gp5 (l8 - crf9) 0x06 gp6 (l8 - crfa) 0x08 soft power enable register 1 (l8-crb0) 0x09 soft power enable register 2 (l8-crb1) 0x0a soft power status register 1 (l8-crb2) 0x0b soft power status register 2 (l8-crb3) note 1: these registers can also be accessed through the configuration registers l8 - crxx, as shown, when the fdc37b72x is in the configurat ion state. gpio configuration each gpio port has an 8-bit configuration register that controls the behavior of the pin. the gpio configuration registers are only accessible when the fdc37b72x is in the c onfiguration state; more information can be found in the configuration section of this specification. each gpio port may be configured as either an input or an output. if the pin is configured as an output, it can be progra mmed as open-drain or push-pull. inputs and outpu ts can be configured as non-inverting or inverting and can be programmed to generate an interrupt. gpio ports can also be configured as a pre-defined alternate downloaded from: http:///
123 function. bit[0] of each gpio configuration register determines the port direction, bit[1] determines the signal polarit y, bits[4:3] select the port function, bit[5] enables the interrupt, and bit[7] determines the output driver type select. the gpio configuration register output type select bit[7] applies to gpio functions, the watchdog timer wdt, the led and the nsmi alternate functions. the basic gp io configuration options are summarized in table 53. for alternate functions, the pin direction is set and controlled internally, r egardless of the state of the gpio direction bit[0]. also, selected alternate input functions cannot be inverted, regardless of the state of the gpio polarity bit[1], except for the eeti function. the interrupt channel for the group interrupts is selected by the gp_int[2:1] configuration registers defined in the fdc37b72x configuration register section. the group interrupts are the "ored" function of t he group interrupt enabled gpio ports and will represent a standard isa interrupt (edge high). gpio group 1 and 2 interrupts can generate smi events, wake-up events through the soft power management logic, and sci/pme events. see the acpi, pme and smi section for details. when the group interrupt is enabled on a gpio input port, the interrupt circuitry contains a selectable digital debounce filt er so that switches or push-buttons may be directly connected to the chip. the debounce filters reject signals with pulse widths 1ms and are enabled per interrupt group in the gp_int[2:1] conf iguration registers. the state of unconnected gpio alternate input functions is inactive. for example, if bits[4:3] in ld8 -crcb are not 00, i.e. nromcs is not the selected function for gp53, internally the state of nromcs is inactive, 1. downloaded from: http:///
124 table 53 - gpio configuration summary selected function direction bit polarity bit group int. enable bit description b0 b1 b5 gpio 0 0 0 pin is a non-inverted output with the interrupt disabled. 0 0 1 pin is a non-inverted output with the interrupt enabled. 0 1 0 pin is an inverted output with the interrupt disabled. 0 1 1 pin is a inverted output with the interrupt enabled. 1 0 0 pin is a non-inverted input with the interrupt disabled. 1 0 1 pin is a non-inverted input with the interrupt enabled. 1 1 0 pin is an inverted input with the interrupt disabled. 1 1 1 pin is a inverted input with the interrupt enabled. alt. x 1 0 0 non-inverted alternate function with interrupt disabled. 0 1 non-inverted alternate function with interrupt enabled. 1 2 0 alternate output functions are inverted, alternate input functions are non-inverted; interrupts are disabled. 1 alternate output functions are inverted, alternate input functions are non-inverted; interrupts are enabled. note 1: for alternate function select s, the pin direction is set and contro lled internally; i.e., regardless of the state of the gpio configur ation register direction bit. note 2: for alternate function selects, input functi ons cannot be inverted, regardl ess of the state of the gpio polarity bit, except for the eeti function. downloaded from: http:///
125 gpio operation the operation of the gpio ports is illustrated in figure 4 . note: figure 4 is for illustration purposes only and is not intended to sugges t specific implementation details. when a gpio port is programmed as an input, reading it through the gpio data register latches either the inverted or non-inverted logic value present at the gpio pin. writing to a gpio port that is programmed as an input has no effect (table 54). when a gpio port is programmed as an output, the logic value or the inverted logic value that has been written into the gpio dat a register is output to the gpio pin. reading from a gpio port that is programmed as an output re turns the last value written to the data register (table 54). table 54 - gpio read/write behavior host operation gpio input port gpio output port read latched value of gpio pin last write to gpio data register write no effect bit placed in gpio data register gpio pin gpio data register bit-n sd-bit gpx_nior gpio confi g uration register bit-1 ( polarit y) gpio configuration re g ister bit-2 or 5 (group int. enable) gpio configuration register bit-0 (input/output) gp group interrupts (1 or 2) 0 1 1 0 d-type transparent gpx_niow dq qd figure 4 - gpio function illustration downloaded from: http:///
126 watch dog timer the fdc37b72x contains a watch dog timer (wdt). the watch dog time-out status bit may be mapped to an interrupt through the wdt_cfg configuration register. it can also be brought out on the gp12 or gp63 pins by programming the corresponding gpio configuration register. the fdc37b72x's wdt has a programmable time-out ranging from 1 to 255 minutes with one minute resolution, or 1 to 255 seconds with 1 second resolution. the units of the wdt timeout value are selected via bit[7] of the wdt_timeout register (ld8:crf1.7). the wdt time-out value is set through the wdt_val configuration register. setting the wdt_val register to 0x00 disables the wdt function (this is its power on default). setting the wdt_val to any other non-zero value will cause the wdt to reload and begin counting down from the value loaded. when the wdt count value reaches zero the counter stops and sets the watchdog time-out status bit in the wd t_ctrl configuration register. note: regardless of the current state of the wdt, the wdt time-out status bit can be directly set or cleared by the host cpu. there are three system events which can reset the wdt. these are a keyboard interrupt, a mouse interrupt, or i/o reads/writes to address 0x201 (the internal or an ex ternal joystick port). the effect on the wdt fo r each of these system events may be individually enabled or disabled through bits in the wdt_cfg configuration register. when a system event is enabled through the wdt_cfg register, t he occurrence of that event will cause the wdt to reload the value stored in wdt_val and reset the wdt time-out status bit if set. if all three system events are disabled the wdt will inevitably time out. the watch dog timer may be configured to generate an interrupt on the rising edge of the time-out status bit. the wdt interrupt is mapped to an interrupt channel through the wdt_cfg configuration register. when mapped to an interrupt the interrupt reques t pin reflects the value of the wdt time-out status bit. the host may force a watch dog time-out to occur by writing a "1" to bit 2 of the wdt_ctrl (force wd time-out) configurati on register. writing a "1" to this bit forces the wdt count value to zero and sets bit 0 of the wdt_ctrl (watch dog status). bit 2 of the wdt_ctrl is self-clearing. led the fdc37b72x can directly drive an led using the alternate function of gp13 or gp61 (only one may be used at at time). these pins are active under vtr power so the led may be used in any system power state. the gpio used for the led will initially default to an input; the corresponding gpio configuration regist er must be programmed to configure the pin for the led function and as a push pull or an open drain output. however, under vtr power the led must be configured as open drain, since the pin c annot drive current under vtr power. the polarity bit may be chosen as either non-inverted or inverted (active high or active low). the led can be turned on and off or toggled at a 1 hertz rate with a 50 percent duty cycle. when the gp13 or gp61 pin is configured as a non- inverted, open drain output and the led function is chosen, the led may be turned on by writing 1 the gp1 register bit 3 or the gp6 register bit 1. clearing these bits will then turn the led off. the led may be toggled as described below. note that the gpio can control the led in its default gpio function, but it may only toggle if the led function is chosen. setting bit 1 of the wdt_ctrl configuration register will cause the po wer led output driver to toggle at 1 hertz with a 50 percent duty cycle. when this bit is cleared the power led output will drive continuously unless it has been configured to toggle on watch dog time-out conditions. setting bit 3 of the wdt_cfg conf iguration register will cause the power led output driver to toggle at 1 hertz with a 50 percent duty cycle whenever the wdt time-out status bit is set. the truth table downloaded from: http:///
127 below clarifies the conditions for which the power led will toggle. table 55 - led toggle wdt_ctrl bit[1] led toggle wdt_cfg bit[3] power led toggle on wdt wdt_ctrl bit[0] wdt t/o status bit led state 1 x x toggle 0 0 x continuous 0 1 0 continuous 0 1 1 toggle downloaded from: http:///
128 8042 keyboard controller description a universal keyboard controller designed for intelligent keyboard management in desktop computer applications is implemented. the universal keyboard controller uses an 8042 microcontroller cpu core. this section concentrates on the enhanc ements to the 8042. for general information about the 8042, refer to the "hardware description of the 8042" in the 8-bit embedded controller handbook. kirq is the keyboard irq mirq is the mouse irq port 21 is used to create a gatea20 signal from the fdc37b72x. 8042a p27p10 p26 tst0 p23 tst1 p22 p11 kdat kclk mclk mdat keyboard and mouse interface ls05 downloaded from: http:///
129 keyboard isa interface the fdc37b72x isa interface is functionally compatible with the 8042-style host interface. it consists of the d0-7 data bus; the nior, niow and the status register, i nput data register, and output data register. table 48 shows how the interface decodes the control signals. in addition to the above signals, the host interface includes keyboard and mouse irqs. table 56 - isa i/o address map isa address niow nior block function (note 1) 0x60 0 1 kdata keyboard data write (c/d=0) 1 0 kdata keyboard data read 0x64 0 1 kdctl keyboard command write (c/d=1) 1 0 kdctl keyboard status read note 1: these registers consist of three separate 8 bit registers. status, da ta/command write and data read. keyboard data write this is an 8 bit write only register. when written, the c/d status bit of the status register is cleared to zero and the ibf bit is set. keyboard data read this is an 8 bit read only register. if enabled by "enable flags", when read, the kirq output is cleared and the obf flag in t he status register is cleared. if not enabl ed, the kirq and/or auxobf1 must be cleared in software. keyboard command write this is an 8 bit write only register. when written, the c/d status bit of the st atus register is set to one and the ibf bit is set. keyboard status read this is an 8 bit read only register. refer to the description of the status register for more information. cpu-to-host communication the fdc37b72x cpu can write to the output data register via register dbb. a write to this register automatically sets bit 0 (obf) in the status register. see table 49. table 57 - host interface flags 8042 instruction flag out dbb set obf, and, if enabled, the kirq output signal goes high downloaded from: http:///
130 host-to-cpu communication the host system can send both commands and data to the input data register. the cpu differentiates between commands and data by reading the value of bit 3 of the status register. when bit 3 is "1", the cpu interprets the register contents as a command. when bit 3 is "0", the cpu interprets the regist er contents as data. during a host write operation, bit 3 is set to "1" if sa2 = 1 or reset to "0" if sa2 = 0. kirq if "en flags" has been executed and p24 is set to a one: the obf flag is gated onto kirq. the kirq signal can be connect ed to system interrupt to signify that the fdc37b72x cpu has written to the output data regi ster via "out dbb,a". if p24 is set to a zero, kirq is forced low. on power-up, after a valid rst pulse has been delivered to the device, kirq is reset to 0. kirq will normally reflects the status of writes "dbb". (kirq is normally selected as irq1 for keyboard support.) if "en flags has not b een executed: kirq can be controlled by writing to p24. writing a zero to p24 forces kirq low; a high forces kirq high. mirq if "en flags" has been executed and p25 is set to a one:; ibf is inverted and gated onto mirq. the mirq signal can be connected to system interrupt to signify that the fdc37b72x cpu has read the dbb register. if "en flags has not been executed, mirq is controlled by p25, writing a zero to p25 forces mirq low, a high forces mirq high. (mirq is normally selected as irq12 for mouse support). gate a20 a general purpose p21 is used as a software controlled gate a20 or user defined output. external keyboard and mouse interface industry-standard pc-at-compatible keyboards employ a two-wire, bidirectional ttl interface for data transmission. several sources also supply ps/2 mouse products that employ the same type of interface. to facilit ate system expansion, the fdc37b72x provides four signal pins that may be used to implement this interface directly for an external keyboard and mouse. the fdc37b72x has four high-drive, open-drain output, bidirectional port pi ns that can be used for external serial interfaces , such as isa external keyboard and ps/2-type mouse interfaces. they are kclk, kdat, mclk, and mdat. p26 is inverted and output as kclk. the kclk pin is connected to test0. p2 7 is inverted and output as kdat. the kdat pin is connected to p10. p23 is inverted and output as mclk. the mclk pin is connected to test1. p22 is inverted and output as mdat. the mdat pin is connected to p11. note: external pull-ups may be required. keyboard power management the keyboard provides support for two power- saving modes: soft powerdown mode and hard powerdown mode. in soft powerdown mode, the clock to the alu is st opped but the timer/counter and interrupts are still active. in hard power down mode the clock to the 8042 is stopped. soft power down mode this mode is entered by executing a halt instruction. the execut ion of program code is halted until either reset is driven active or a data byte is written to the d bbin register by a master cpu. if this mode is exited using the interrupt, and the ibf interrupt is enabled, then program execution resumes with a call to the interrupt routine, otherwise the next instruction is executed. if it is exited using reset then a normal reset sequence is initiated and program execution starts from program memory location 0. hard power down mode hard power down mode is entered by executing a stop instruction. disab ling the oscillator driver cell stops the oscillator. when either reset is driven active or a data byte is written to the dbbin register by a master cpu, this mode will be exited downloaded from: http:///
131 (as above). however, as the oscillator cell will require an initialization time, either reset must be held active for sufficient time to allow the oscillator to stabilize. program execution will resume as above. interrupts the fdc37b72x provides the two 8042 interrupts, the ibf and the timer/counter overflow. memory configurations the fdc37b72x provides 2k of on-chip rom and 256 bytes of on-chip ram. register definitions host i/f data register the input data and out put data registers are each 8 bits wide. a write to this 8 bit register will load the keyboard data read buffer, set the obf flag and set the kirq output if enabled. a read of this register will read t he data from the keyboard data or command write buffer and clear the ibf flag. refer to the ki rq and status register descriptions for more information. host i/f status register the status register is 8 bits wide. table 58 shows the contents of the status register. table 58 - status register d7 d6 d5 d4 d3 d2 d1 d0 ud ud ud ud c/d ud ibf obf status register this register is cleared on a reset. this register is read-only for the host and read/write by the fdc37b72x cpu. ud writable by fdc37b72x cpu. these bits are user-definable. c/d (command data)-this bit specifies whether the input data register contains data or a command (0 = data, 1 = command). during a host data/command write operat ion, this bit is set to "1" if sa2 = 1 or reset to "0" if sa2 = 0. ibf (input buffer full)- this flag is set to 1 whenever the host system writes data into the input data register. setting this flag activates the fdc37b72x cpu's nibf (mirq) interrupt if enabled. when the fdc37b72x cpu reads the input data register (dbb), this bit is automatically reset and the interrupt is cleared. there is no output pin associated with this internal signal. obf (output buffer full) - this flag is set to whenever the fdc37b72x cpu write to the output data register (dbb). when the host system reads the output data register, this bit is automatically reset. external clock signal the fdc37b72x keyboard controller clock source is a 12 mhz clock generated from a 14.318 mhz clock. the reset pulse must last for at least 24 16 mhz clock periods. the pulse-width requirement applies to both internally (vcc por) and externally generated reset signals. in powerdown mode, the external clock signal is not loaded by the chip. default reset conditions the fdc37b72x has one source of reset: an external reset via the reset_drv pin. refer to table 59 for the effect of each type of reset on the internal registers. table 59 - resets description hardware reset (reset) downloaded from: http:///
11 description hardware reset (reset) kclk input kdat input mclk input mdat input host i/f data reg n/a host i/f status reg 00h n/a: not applicable gatea20 and keyboard reset the fdc37b72x provides two options for gatea20 and keyboard reset: 8042 software generated gatea20 and kreset and port 92 fast gatea20 and kreset. port 92 fast gatea20 and keyboard reset port 92 register this port can only be read or written if port 92 has been enabled via bit 2 of the krst_ga20 register (logical device 7, 0xf0) set to 1. this register is used to support the alternate reset (nalt_rst) and alternate a20 (alt_a20) functions. name port 92 location 92h default value 24h attribute read/write size 8 bits downloaded from: http:///
133 port 92 register bit function 7:6 reserved. returns 00 when read 5 reserved. returns a 1 when read 4 reserved. returns a 0 when read 3 reserved. returns a 0 when read 2 reserved. returns a 1 when read 1 alt_a20 signal control. writing a 0 to this bit causes the alt_a20 signal to be driven low. writing a 1 to this bit c auses the alt_a20 signal to be driven high. 0 alternate system reset. this read/writ e bit provides an alternate system reset function. this function provides an alte rnate means to reset the system cpu to effect a mode switch from protected vi rtual address mode to the real address mode. this provides a faster means of reset than is provided by the keyboard controller. this bit is set to a 0 by a syst em reset. writing a 1 to this bit will cause the nalt_rst signal to pulse active (low) for a minimum of 1 s after a delay of 500 ns. before another nalt_rst pulse c an be generated, this bit must be written back to a 0. ngatea20 8042 p21 alt_a20 system na20m 0 0 0 0 1 1 1 0 1 1 1 1 bit 0 of port 92, whic h generates the nalt_rst signal, is used to reset the cpu under program control. this signal is anded together externally with the reset signal (nkbdrst) from the keyboard controller to provide a software means of resetting the cpu. th is provides a faster means of reset than is provided by the keyboard controller. writing a 1 to bit 0 in the port 92 register causes this signal to pulse low for a minimum of 6s, after a delay of a minimum of 14s. before another nalt_rst pulse can be generated, bit 0 must be set to 0 either by a system reset of a write to port 92. upon reset, this signal is driven inactive high (bit 0 in the port 92 register is set to 0). if port 92 is enabled, i.e., bit 2 of krst_ga20 is set to 1, then a pulse is generated by writing a 1 to bit 0 of the port 92 register and this pulse is anded with the pulse generated from the 8042. this pulse is output on pin kreset and its polarity is controlled by the gpi/o polarity configuration. downloaded from: http:///
134 bit 1 of port 92, the alt_a20 signal, is used to force na20m to the cpu low for support of real mode compatible software. this signal is externally ored with the a20gate signal from the keyboard controller and cpurst to control the na20m input of the cpu. writing a 0 to bit 1 of the port 92 register forces alt_a20 low. alt_a20 low drives na20m to the cpu low, if a20gate from the keyboard controller is also low. writing a 1 to bit 1 of the port 92 register forces alt_a20 high. alt_a20 high drives na20m to the cpu high, regardless of the state of a20gate from the ke yboard controller. upon reset, this signal is driven low. 8042 p17 functions 8042 function p17 is implemented as in a true 8042 part. reference the 8042 spec for all timing. a port signal of 0 drives the output to 0. a port signal of 1 causes the port enable signal to drive the output to 1 within 20-30nsec. after several (# tbd) clocks, the port enable goes away and the internal 90a pull-up maintains the output signal as 1. in 8042 mode, the pins can be programmed as open drain. when programmed in open drain mode, the port enables do not come into play. if the port signal is 0 the output will be 0. if the port 8042 p92 pulse gen kbdrst krst_ga20 bit 2 bit 0 p20 krst nalt_rst 6us 14us ~ ~ 6us 14us ~ ~ note: when port 92 is disabled, writes are ignored and reads return undefined values. kreset generation downloaded from: http:///
136 signal is 1, the output tris tates: an external pull-up can pull the pin high, an d the pin can be shared i.e., p17 and nsmi can be externally tied together. in 8042 mode, the pins cannot be programmed as input nor inverted through the gp configuration registers. 0ns 250ns 500ns clk aen naen 64=i/o addr n64 niow na dd1 ndd1 ncntl niow' niow+n64 afterd1 nafterd1 60=i/o addr n60 niow+n60=b nafterd1+b d[1] ga20 gate a20 turn-on sequence timing when writing to the command and data port with hardware speedup, the iow timing shown in the figure titled iow timing for port 92 in the timing diagrams section is used. this setup time is only required to be met when using hardware speedup; the dat a must be valid a minimum of 0 nsec from the leading edge of the write and held throughout t he entire write cycle. downloaded from: http:///
136 soft power management this chip employs soft power management to allow the chip to enter low power mode and to provide a variety of wakeup events to power up the chip. this technique allows for software control over powerdown and wakeup events. in low power mode, the chip runs off of the trickle voltage, vtr. in this m ode, the chip is ready to power up from either the power button or from one of a number of wakeup ev ents including pressing a key, touching the mouse or receiving data from one of the uarts. the alarm can also be set to power up the system at a predetermined time to perform one or more tasks. the implementation of soft power management is illustrated in figure 11. a high to low transition on the button input or on any of the enabled wakeup events (spx) causes the npoweron output to go active low which turns on the main power supply. even if the power supply is completely lost (i.e., vtr is not present) the power supply can still be turned on upon the return of vtr. this is accomplished by a vtr power on reset if the vtr_por_en bit is enabled. the chip can also be programmed to always stay off when the ac power returns if the vtr_por_off bit is enabled. these bits are located in the soft power enable register 2 in logical device 8 at 0xb1. the button input can be used to turn off the power supply after a debounce delay. the power supply can also be turned off under software control (via a write to register wdt_ctrl with bit 7 set). configuration registers l8-cr_b0 and l8- cr_b1 select the wake-up events (spx). the configuration registers l8-cr_b2 and l8- cr_b3 indict the wake- up event status. the possible wake-events are: ? uart1 and uart 2 ring indicator pin ? keyboard and mouse clock pin ? group interrupt 1, group interrupt 2 ? irrx2 input pin ? uart 1 and uart 2 receive data pin ? nring pin ? power button input pin ? vtr_por downloaded from: http:///
137 figure 5 - soft power management functional diagram note 1: all soft power management functions run off of vtr. when vtr is not present, vbat supplies power to flip flop 1. note 2: flip flop 1 is battery backed-up so that it returns the last valid state of the machine. note 3: a battery backed-up enable bit in the alarm contro l register can be set to force flip flop 1 to come up off after a vtr por, the vtr_por_off bit. a similar bit can be set to force flip flop 1 to come up on after a vtr por, the vtr_por_en bit. these bits are in the soft power enable register 2 in logical device 8 at 0xb1, defined as follows. bit 4 C vtr_por_off if vtr_por_off is set, the npoweron pin will go i nactive (float) and the main power (vcc) will remain off when the vtr por occurs. th e software must not set vtr_por_off and vtr_por_en at the same time. bit 6 - vtr_por_en if vtr_por_en is set, the npoweron pin will go active (low) and the machine will power-up as soon as a vtr por occurs. the software must not set vtr_por_off and vtr_por_en at the same time. registers a transition on the button input, or on any enabled inputs causes the npoweron output to go active low. a low pulse on the soft power off signal, a vbat por, a vtr por with v bat<1.2v, or power button override event causes npoweron to float. ed;pg = edge detect, pulse generator ed;l = edge detect and latch en1 enx d q clr button input sp1 spx open collector type output soft power off npoweron vtr nspoff1 nspoff1 ed; pg ed; l ed; l alarm off_en nspoff1 nspoff delay1 off_dly delay2 nbint off_dly logic l button v bat por al_rem_en flip flop 1 vtr por vtr_por_en logic logic override timer pwrbtnor_sts pwrbtnor_en nspoff1 v tr por with vbat<1.2v v tr_ por_off vtr por spx downloaded from: http:///
138 the following registers can be accessed when in configuration mode at logical device 8, registers b0-b3, b8 and f4, and when not in configuration they c an be accessed through the index and data register. all soft power management configuration registers are battery backed up and are reset on vbat por. soft power enable registers soft power enable register 1 (configuration register b0, logical device 8) this register contains the enable bits for the wake-up function of the npoweron bit. when enabled, these bits allow their corresponding function to turn on power to the system. soft power enable register 2 (configuration register b1, logical device 8) this register contains additional enable bits for the wake-up function of the npoweron bit. when enabled, these bits allow their corresponding function to turn on power to the system. it also contains the vtr_por_en and vtr_por_off bits, as well as the off_en bit, which is defined as follows: after power up, this bit defaults to 1, i.e., enabled. this bit allows the software to enable or disable the button control of power off. soft power status registers soft power status register 1 (configuration register b2, logical device 8) this register contains t he status for the wake-up events. note: the stat us bit gets set if the wakeup event occurs, w hether or not it is enabled as a wakeup function by setting the corresponding bit in soft power enable register 1. however, only the enabled wakeup functions will turn on power to the system. soft power status register 2 (configuration register b3, logical device 8) this register contains additional status for the wake-up events. note: the status bit gets set if the wakeup event occurs, whether or not it is enabled as a wakeup function by setting the corresponding bit in soft power enable register 2. however, only the enabled wakeup functions will turn on power to the system. soft power control registers wdt_ctrl (configuration register f4, logical device 8) this register is used for soft power management and watchdog timer control. bits [7:5] are for soft power management: spoff, restart_cnt, stop_cnt. delay 2 time set register (configuration register b8, logical device 8) this register is used to set delay 2 to value from 500msec to 32sec. the default value is 500msec. downloaded from: http:///
139 button override feature the power button has an override event as required by the acpi spec ification. if the user presses the power button for more than four seconds while the system is in the working state, a hardware event is generated and the system will transition to the off st ate. there are status bits and enable bits associated with this feature in the pm1_blk regist ers. see the acpi section. this override event utilizes power button logic to determine that the power button (button_in) has been pressed for more that four seconds. the override enable/disable bit, pwrbtnor_en, allows this override function to be turned on/off. if enabled, this override event will result in setting the override status bit, pwrbtnor_sts (to be cleared by writing a 1 to its bit position - writing a 0 has no effect), clear ing the regular button status bit, pwrbtn_sts, and generating an event to be routed into the soft power management logic to turn off the system. the override status bit aler ts the system upon power- up that an override event was used to power down the system, and will be used to properly power-up the system. figure 11 shows the soft power management logic with the override timer path from the button input. the override timer counts while the button is held (in the present implementation this would be when the button input is high) and is cleared upon release of the button. it has a 0.5 second or faster resolution (run off of the 32khz clock divided down) and the minimum time for triggering the override power down is four seconds, with a maximum of 4.5 seconds. the timer output will pulse t he clear on the flip flop 1. figure 12 illustrates the timing of the blanking period relative to button_in and npoweron for the override event. downloaded from: http:///
140 figure 6 - blanking period button_in npoweron blanking period v cc 4+ sec release sec 4 sec 4 downloaded from: http:///
141 acpi/pme/smi features acpi features the fdc37b72x supports acpi as described in this section. these features comply with the acpi specificati on, revision 1.0. legacy/acpi select capability this capability consists of an smi/sci switch which is required in a sy stem that supports both legacy and acpi power management models. this is due to the fact that the system software for legacy power management consists of the smi interrupt handler while for acpi it consists of the acpi driver (sci in terrupt handler). this support uses logical device a at 0x0a to hold the address pointers to the acpi power management register bl ock, pm1_blk, which consists of run-time r egisters. included in the pm1_blk is an enable bit, sci_en, to allow the sci interrupt to be generated upon an enabled sci event. this sci interrupt can be switched out to the npme/sci pin or routed to one of the parallel interrupts. t he polarity and output type (open collector or push- pull) of the sci is selected through the irq mux register. the software power management events (those that generate an smi in legacy mode and an sci in acpi mode) are cont rolled by the en_smi and sci_en bits. the sci enable bit, sci_en, is located in the pm1_cntrl register, bit 0. this bit is used in conjunction with en_smi, bit 7 of the smi enable register 2, to enable either sci or smi (or both). for legacy power management, the en_smi bit is used; if set, it routes the power management events to the sm i interrupt logic. for acpi power management, the sci_en bit is used; if set, it rout es the power management events to the sci interrupt logic. power button with override the power button has a status and and enable bit in the pm1_blk of registers to provide an sci upon the button press. the power button can also turn the system on and off through the soft power management logic. the power button also has an override event as required by the acpi specification. see the soft power management section. this override event is described as follows: if the user presses the power button for more than 4 seconds while the system is in the worki ng state, a hardware event is generated and the system will transition to the off state. there ar e status and enable bits associated with this f eature in the pm1_blk registers. general purpose acpi events the general purpose acpi events are enabled through the sci_en1 bit in the gpe_en register. this bit, if set, allows any of the enabled pme events to generate an sci. in addition, if the devint_en bit in the pme_en 1 register is set, and if the en_smi_pme bit in the smi_en 2 register is set, then any of the smi events can also generate an sci. see the sci/pme and smi/pme logic diagrams below. device sleep states each device in the fdc37b72x supports two device sleep states, d0 (on) and d3 (off). with all devices off, the part is powered either by main power (vcc) or standby power (vtr), depending on the system sleep state. in both cases, the part can provide wak eup capability through the soft power management logic and generate a npme or nsci. in an acpi system, the devices are powered on and off through control methods. downloaded from: http:///
142 wake events wake events are events that turn power on (activate npoweron out put) if enabled. these events can also be enabled as smi, sci and npme events as shown in the following table. in addition, these wake events set the wak_sts bit if enabled (see acpi pm1_sts2 register description). wake events input to soft power management smi/sci/pme generation pins kdat kdat smi/sci/pme mdat mdat smi/sci/pme irrx2 irrx2 smi/sci/pme rxd2/irrx rxd2/i rrx smi/sci/pme rxd1 rxd1 smi/sci 1 /pme 1 nri1 nri1 smi/sci/pme nri2 nri2 smi/sci/pme nring nring smi/sci/pme button button smi/sci 2 /pme 1 gp10-17 3 gpint1 smi/sci 1 /pme gp50-54, gp60-67 gpint2 smi/sci 1 /pme 1 interna l signals vtr por vtr por sci note 1: these sci/pme events are smi events that are enabled through devint_en. note 2: these sci events have status and enable bits in the pm1 registers. note 3: the polarity of the edge t hat causes the event is programm able through the polarity bit in the gpio configuration registers. t he default is the low-to-high edge. the following are smi events t hat are not wake events: ? floppy interrupt ? parallel port interrupt ? wdt ? p12 any wakeup logic that affects t he configuration of t he wakeup events is impl emented so that the configuration of the wakeup events is retained (in the event of total power loss) upon vtr por. downloaded from: http:///
143 pme support the fdc37b72x offers support for pci power management events (pmes). a power management event is reques ted by a pci function via the assertion of the npme signal. the assertion and deassertion of npme is asynchronous to the pci clock. in the fdc37b72x, active transitions on the ring indicator inputs nri1 and nri2 or the nring pin, active keyboard-data edges, acti ve mouse-data edges and gpios gp10-gp17 can directly assert the npme signal. in addition, if the devint_en bit in the pme_en 1 register is set, and if the en_smi_pme bit in the smi_en 2 register is set, then any of the smi event s can also generate a npme. see the sci/pme and smi/pme logic diagrams below. npme functionality is c ontrolled by the runtime registers at +ch through +11h. the pme enable bit, pme_en, globally controls pme wake-up events. when pme_en is inactive, the npme signal can not be asserted. when pme_en is asserted, any wake source whose individual pme wake enable register bit is asserted can cause npme to become asserted. the pme wake status register indicates which wake source has asserted the npme signal. the pme status bit, pme_sts, is asserted by active transitions of pme wake sources. pme_sts will become asserted independent of the state of the global pme enable, pme_en. in the fdc37b72x the npme pin is an open drain, active low, driver. the fdc37b72x npme pin is fully isolated from other external devices that might pull the pci np me signal low; i.e., the pci npme signal is capable of being driven high externally by another active device or pullup even when the the fdc37b72x vdd is grounded, providing vtr power is active. the fdc37b72x npme driver sinks 6ma at .55v max (see section 4.2.1.1 dc specifications, page 122, in the pci local bus specification, revision 2.1). acpi, pme and smi registers logical device a in the configuration section contains the address point er to the acpi power management register block, and pm1_blk. these are run-time regi sters; included in the pm1_blk is an enable bit to allow the sci group interrupt to be routed to any interrupt or onto the npme/sci pin. note: see irq mux control register for sci/pme/smi selection function and pin configuration bits. register description the acpi register model consists of a number of fixed register blocks that perform designated functions. a register blo ck consists of a number of registers that per form status, enable and control functions. the ac pi specification deals with events (which have an associated interrupt status and enable bits, and sometimes an associated control functi on) and control features. the status registers illustrate what defined function is requesting acpi interrupt services (sci). any status bit in the acpi specification has the following attributes: a. status bits are only set through some defined hardware event. b. unless otherwise not ed, status bits are cleared by writing a high to that bit position, and upon vtr por. writing a 0 has no effect. c. status bits onl y generate interrupts while their associated bit in the enable register is set. d. function bit positi ons in the status register have the same bit position in the enable register (there are exceptions to this rule, special status bits have no enables). note that this implies t hat if the respective enable bit is reset and the hardware event occurs, the respective status bit is set, however no interrupt is generated until the enable bit is set. this allows software to test t he state of the event (by examining the status bi t) without necessarily generating an interrupt. there are a special class of status bits that hav e no respective enable bit, these are called out specifically, and the downloaded from: http:///
144 respective enable bit in the enable register is marked as reserved for these special cases. the enable registers allow the setting of the status bit to generate an interrupt. as a general rule there is an enable bi t in the enable register for every status bit in the status register. the control register provides special controls for the associated event, or specia l control features that are not associated with an interrupt event. the ordering of a register block is the status registers, followed by enable registers, followed by control registers. table 60 and 61 list the pm1/gpe and pme/smi/msc register blocks and the locations of the registers contained in these blocks. all of these registers are powered by vtr and battery backed-up and are reset on vbat por. wakeup event configuration is retained by battery power to preserve the confi guration of the wakeup functions that were progr ammed prior to the loss of vtr upon its return, the soft power management registers, pme, sci, smi registers and gpio registers are all powered by the battery. these registers are reset to their default values only on vbat por. these registers are described in the sections below. downloaded from: http:///
145 register block the registers in this block are powered by vtr and battery backed up. table 60 - pm1/gpe register block register size address pm1_sts 1 8 pm1_sts 2 8 +1h pm1_en 1 8 +2h pm1_en 2 8 +3h pm1_cntrl 1 8 +4h pm1_cntrl 2 8 +5h reserved 8 +6h reserved 8 +7h gpe_sts 1 8 +8h gpe_en 1 8 +9h reserved 8 +ah reserved 8 +bh table 61 - pme/smi/msc register block register size address pme_sts 1 8 < pm1_blk>+ch pme_sts 2 8 < pm1_blk>+dh pme_en 1 8 < pm1_blk>+eh pme_en 2 8 < pm1_blk>+fh pme_sts 8 < pm1_blk>+10h pme_en 8 < pm1_blk>+11h smi_sts 1 8 < pm1_blk>+12h smi_sts 2 8 < pm1_blk>+13h smi_en 1 8 < pm1_blk>+14h smi_en 2 8 < pm1_blk>+15h msc_sts 8 < pm1_blk>+16h reserved 8 < pm1_blk>+17h table 62 shows the block size and range of base addresses for each block. table 62 - register block attributes block name block size base address range pm1_blk 24-bytes 0-fff downloaded from: http:///
146 acpi registers in the fdc37b72x, the pme wakeup events can be enabled as sci events through the sci_sts1 and sci_en1 bits in the gpe status and enable regist ers. see pme interface and smi/pme/sci logic sections. power management 1 status register 1 (pm1_sts 1) register location: system i/o space default value: 00h on vbat por attribute: read/write (note 0) size: 8-bits bit name description 0-7 reserved reserved. these bits always return a value of zero. note 1: this bit is set by hardware and can only be cleared by software writing a one to this bit position and by vbat por. writing a 0 has no effect. downloaded from: http:///
147 power management 1 status register 2 (pm1_sts 2) register location: +1h system i/o space default value: 00h on vbat por attribute: read/write (note 0) size: 8-bits bit name description 0 pwrbtn_sts this bit is set when t he button_in signal is asserted. in the system working state, while pwrbtn_en and pwrbtn_sts are both set an sci interrupt event is raised. in the sleeping or soft off state, a wake-up event is generated (regardless of the setting of pwrbtn_en) (note 2). this bit is only set by hardware and is reset by software writing a one to this bit position, and by vbat por. writi ng a 0 has no effect. it is also reset as follows: if pwrbtnor_en is set, and if the button_in signal is held asserted for more than four seconds, then this bit is cleared, the pwrbtnor_sts bit is set and the system will transition into the so ft off state (npoweron floats). 1 reserved reserved. 2 reserved reserved 3 pwrbtnor_sts this bit is set when the power switch over-ride function is set: if pwrbtnor_en is set, and if the button_in signal is held asserted for more than four seconds. hardware is also required to reset the pwrbtn_sts when issuing a power switch over-ride function. (note 1) 4-6 reserved reserved. these bits always return a value of zero. 7 wak_sts this bit is set when the system is in the sleeping state and an enabled wakeup event occurs. this bit is set on the high-to-low transition of npoweron, if the wak_ctrl bit in the sleep / wake configuration register (0 xf0 in logical device a) is cleared. if the wak_ctrl bit is set, then any enabled wakeup event will also set the wak_sts bit in addition to the high-to- low transition of npoweron. it is cleared by writing a 1 to its bit location when npoweron is active (low). upon setting this bit, the system will transition to t he working state. (note 1) note 1: this bit is set by hardware and can only be cleared by software writing a one to this bit position and by vbat por. writing a 0 has no effect. nore 2: in the present implement ation of button_in, pre ssing the button will always wake the machine (i.e., activate npoweron). downloaded from: http:///
148 power management 1 enable register 1 (pm1_en 1) register location: +2 system i/o space default value: 00h on vbat por attribute: read/write (note 0) size: 8-bits bit name description 0-7 reserved reserved. these bits always return a value of zero. power management 1 enable register 2 (pm1_en 2) register location: +3 system i/o space default value: 00h on vbat por attribute: read/write (note 0) size: 8-bits bit name description 0 pwrbtn_en this bit is used to enabl e the assertion of the button_in to generate an sci event. the pwrbtn_sts bit is set anytime the button_in signal is assert ed. the enable bit does not have to be set to enable the setting of the pwrbtn_sts bit by the assertion of the button_in signal. 1-7 reserved reserved. these bits always return a value of zero. power management 1 control register 1 (pm1_cntrl 1) register location: +4 system i/o space default value: 00h on vbat por attribute: read/write (note 0) size: 8-bits bit name description 0 sci_en when this bit is set, then the enabled sci power management events generate an sci interrupt. when this bit is reset power management events do not generate an sci interrupt. 1-7 reserved reserved. these bits always return a value of zero. downloaded from: http:///
149 power management 1 control register 2 (pm1_cntrl 2) register location: +5 system i/o space default value: 00h on vbat por attribute: read/write (note 0) size: 8-bits bit name description 0 reserved reserved. this field always returns zero. 1 pwrbtnor_en this bit controls the power button over-ride function. when set, then anytime the button_in signal is asse rted for more than four seconds the system will transition to the o ff state. when a power button over- ride event occurs, the logic clears the pwrbtn_sts bit, and sets the pwrbtnor_sts bit. 2-4 slp_typx this 3-bit field defines t he type of hardware sl eep state the system enters when the slp_en bit is set to one. when this field is 000 the fdc37b72x will transition the mach ine to the off state when the slp_en bit is set to one. that is, wi th this field set to 000, npoweron will go inactive (float) after a 1-2 clock delay when slp_en is set. this delay is a minimum of one 32khz clock and a maximum of two 32khz clocks (31.25 sec-62.5 sec). when this field is any other value, there is no effect. 5 slp_en this is a write-only bit and reads to it always return a zero. writing 1 to this bit causes the system to sequence into the sleeping state associated with the slp_typx fields after a 1-2 clock delay, if the slp_ctrl bit in the sleep / wake configuration register (0xf0 in logical device a) is cleared. if the slp_ctrl bit is set, do not sequence into the sleeping state associ ated with the slp_typx field, but generate an smi. note: the slp_ en_smi bit in the smi status register 2 is always set upon writing 1 to the slp_en bit. writing 0 to this bit has no effect. 6-7 reserved reserved. this field always returns zero. general purpose event status register 1 (gpe_sts1) register location: +8 system i/o space default value: 00h on vbat por attribute: read/write (note 0) size: 8-bits bit name description 0 sci_sts1 this bit is set when t he device power management events (pme events) occur. when enabled, the se tting of this bit will generate an sci interrupt. (note 1) 1-7 reserved reserved. these bits always return a value of zero. note 1: this bit is set by hardware and can only be cleared by software writing a one to this bit position and by vbat por. writing a 0 has no effect. downloaded from: http:///
150 general purpose event enable register 1 (gpe_en1) register location: +9 system i/o space default value: 00h on vbat por attribute: read/write (note 0) size: 8-bits bit name description 0 sci_en1 when this bit is set, then the enabled device power management events (pme events) will generate an sci interrupt. when this bit is reset, device power management events will not generate an sci interrupt. 1-7 reserved reserved. these bits always return a value of zero. note 0: all bits described as "reserved" in writeabl e registers must be written with the value 0 when the register is written. pme registers the power management event functi on has a pme_status bit and a pme_en bit. these bits are defined in the pci bus power management interface specification, revision 1.0, draft, copyright ? 1997, pci special interest group, mar. 18, 1997. the default states for the pme_status and pme_en bits are controlled by v bat power-on-reset. pme status register (pme_sts) register location: +10h system i/o space default value: 00h on vbat por attribute: read/write (note 0) size: 8-bits d7 d6 d5 d4 d3 d2 d1 d0 default reserved pme_status 0x00 ? the pme_status bit is set when the fdc37b72x would normally assert the pci npme signal, independent of the state of the pme_en bit. only active tr ansitions on the pme wake sources can set the pme_status bit. ? the pme_status bit is read/write-clear. writing a 1 to the pme_ status bit will clear it and cause the fdc37b72x to stop asse rting the npme, if enabled. ? writing a 0 has no effect on the pme_status bit. ? the pme_status bit is reset to 0 during vbat power-on-reset. downloaded from: http:///
151 pme enable register (pme_en) register location: +11h system i/o space default value: 00h on vbat por attribute: read/write (note 0) size: 8-bits d7 d6 d5 d4 d3 d2 d1 d0 default reserved pme_en 0x00 ? setting the pme_en bit to 1 enables t he fdc37b72x to assert the npme signal. ? when the pme_en bit is reset to 0, npme signal assertion is disabled. ? the pme_en bit is reset to 0 during vbat power-on-reset. pme status register 1 (pme_sts 1) register location: +ch system i/o space default value: 00h on vbat por attribute: read/write (note 0) size: 8-bits d7 d6 d5 d4 d3 d2 d1 d0 default devint_st s reserved nring mouse kbd ri1 ri2 reserved 0x00 pme status register 2 (pme_sts2) register location: +dh system i/o space default value: 00h on vbat por attribute: read/write (note 0) size: 8-bits d7 d6 d5 d4 d3 d2 d1 d0 default gp17 gp16 gp15 gp14 gp13 gp12 gp11 gp10 0x00 ? the pme status registers indi cate the state of the individual fdc37b72x pme wake sources, independent of the state of the individual source enables or the pme_en bit. ? if the wake source has asserted a wake event, the associated pme status bit will be 1. the wake source bits in the pme status registers are read/write-clear: an ac tive (1) pme status bit can only be cleared by writing a 1 to the bit. writing a 0 to bits in the pme wake status register has no effect. pme enable register 1 (pme_en1) register location: +eh system i/o space default value: 00h on vbat por attribute: read/write (note 0) size: 8-bits d7 d6 d5 d4 d3 d2 d1 d0 defaul t devint_en reserved nring mouse kbd ri1 ri2 reserved 0x00 downloaded from: http:///
152 pme enable register 2 (pme_en2) register location: +fh system i/o space default value: 00h on vbat por attribute: read/write (note 0) size: 8-bits d7 d6 d5 d4 d3 d2 d1 d0 default gp17 gp16 gp15 gp14 gp13 gp12 gp11 gp10 0x00 ? the pme enable registers enable the individual fdc37b72x wake sources onto the npme bus. ? when the pme enable register bit for a wake source is active (1), if the source asserts a wake event and the pme_en bit is 1, the source will assert the pci npme signal. ? when the pme enable register bit for a wake source is inactive (0), the pme status register will indicate the state of the wake source but will not assert the pci npme signal. smi registers the fdc37b72x implements a group ns mi output pin. the ns mi group interrupt output consists of the enabled interrupts from each of the f unctional blocks in the chip plus other smi events. the interrupts are enabled onto the group nsmi output via the smi enable registers 1 and 2. the nsmi output is then enabled onto the group nsmi out put pin via bit[7] in the smi enable register 2. these smi events can also be enabled as npme/sci events by setting the en _smi_pme bit, bit[6] of smi enable register 2. this register is also used to enable the group nsmi output onto the nsmi serial/parallel irq pin and the routing of 8042 p12 internally to nsmi. smi status register 1 (smi_sts1) register location: +12h system i/o space default value: 00h on vbat por attribute: read/write size: 8-bits name description smi status register 1 default = 0x00 on vbat por this register is used to read the status of the smi inputs. the following bits must be cleared at their source. bit[0] reserved bit[1] pint (parallel port interrupt) bit[2] u2int (uart 2 interrupt) bit[3] u1int (uart 1 interrupt) bit[4] fint (floppy di sk controller interrupt) bit[5] gpint2 (group interrupt 2) bit[6] gpint1 (group interrupt 1) bit[7] wdt (watch dog timer) downloaded from: http:///
153 smi status register 2 (smi_sts2) register location: +13h system i/o space default value: 00h on vbat por attribute: read/write size: 8-bits name description smi status register 2 default = 0x00 on vbat por this register is used to read the status of the smi inputs. bit[0] mint: mouse interrupt. cleared at source. bit[1] kint: keyboard interrupt. cleared at source. bit[2] irint: this bit is set by a transition on the ir pin (rxd2 or irrx2 as selected by bit 6 of configuration regi ster 0xf1 in logical device 5, i.e., after the mux). cleared by a read of this register. bit[3] bint: cleared by a read of this register. bit[4] p12: 8042 p1.2. cleared at source bits[5:6] reserved bit[7] slp_en_smi. the slp_en smi status bit. cleared by a read of this register. (see sleep enable config reg.) 0=no smi due to setting slp_en bit 1=smi generated due to setting slp_en bit. smi enable register 1 (smi_en1) register location: < pm1_blk >+14h system i/o space default value: 00h on vbat por attribute: read/write size: 8-bits name description smi enable register 1 default = 0x00 on vbat por this register is used to enable the different interrupt sources onto the group nsmi output. 1=enable 0=disable bit[0] en_ring note: the pme status bit for ring is used as the smi status bit for ring (see pme status register). bit[1] en_pint bit[2] en_u2int bit[3] en_u1int bit[4] en_fint bit[5] en_gpint2 bit[6] en_gpint1 bit[7] en_wdt downloaded from: http:///
154 smi enable register 2 (smi_en2) register location: < pm1_blk >+15h system i/o space default value: 00h on vbat por attribute: read/write size: 8-bits name description smi enable register 2 default = 0x00 on vbat por this register is used to enable the di fferent interrupt sources onto the group nsmi output, and the group nsmi output onto the nsmi gpi/o pin. unless otherwise noted, 1=enable 0=disable bit[0] en_mint bit[1] en_kint bit[2] en_irint bit[3] en_bint bit[4] en_p12: enable 8042 p1.2 to route internally to nsmi 0=do not route to nsmi 1=enable routing to nsmi. bit[5] reserved bit[6] en_smi_pme: enable the group ns mi output into the pme interface logic. 0= group smi output does not go to pme interface logic 1= enable group smi output to pme interface logic bit[7] en_smi: enable the group nsmi output onto the nsmi pin or serial irq frame (irq2). 0=smi pin floats 1=enable group nsmi output onto nsmi pin or serial irq frame note: the selection of either the nsmi pin or serial irq frame is done via bit 7 of the irq mux control register (0xc0 in logical device 8). downloaded from: http:///
155 either edge triggered interrupts four gpio pins are im plemented that allow an interrupt to be generated on both a high-to-low and a low-to-high edge transition, instead of one or the other as select ed by the polarity bit. the either edge triggered interrupts function as follows: selecting the either edge triggered interrupt (eeti) function for these gpio pins is applicable when the combined interrupt is enabled for the gpio pin (gpint1 for gp11 and gp12, and gpint2 for gp53 and gp54). otherwise, selection of the eeti function will produce no function for the pin. if the eeti function is selected for the gpio pin, then the bits that control i nput/output, polarity and open collector/push-pull have no effect on the function of the pin. however, t he polarity bit does affect the value of the gp bit (i.e., register gp1, bit 2 for gp12). an interrupt occurs if t he status bit is set and the interrupt is enabled. the status bits indicate which of the eeti interr upts transitioned. these status bits are located in the msc_sts register. the status is valid whether or not the interrupt is enabled and whether or not the eeti function is selected for the pin. miscellaneous status register the msc_sts register is implemented as follows to hold the status bits of these four gpios. miscellaneous status register (pm1_sts) register location: +16h system i/o space default value: 00h on vbat por attribute: read/write (note 0) size: 8-bits bit name definition 0 eeti1_sts either edge triggered interrupt input 1 status. this bit is set when an edge occurs on the gp11 pin. this bit is cleared by writing a 1 to this bit position (writing a 0 has no effect). 1 eeti2_sts either edge triggered interrupt input 2 status. this bit is set when an edge occurs on the gp12 pin. this bit is cleared by writing a 1 to this bit position (writing a 0 has no effect). 2 eeti3_sts either edge triggered interrupt input 3 status. this bit is set when an edge occurs on the gp53 pin. this bit is cleared by writing a 1 to this bit position (writing a 0 has no effect). 3 eeti4_sts either edge triggered interrupt input 4 status. this bit is set when an edge occurs on the gp54 pin. this bit is cleared by writing a 1 to this bit position (writing a 0 has no effect). 4 vtrpor_sts this bit is set upon vtr por. this bit is cleared by writing a 1 to this bit position (writing a 0 has no effect). additionally, when the system turns on (npoweron active low) due to a vtr por, then an sci is generated. 5-7 reserved reserved. this bit always returns zero. downloaded from: http:///
156 smi/pme/sci logic the logic for the smi, pme and sci signals is shown in the figures that follow. figure 7 - pme/sci logic pme_en1 register pme_sts1 register pme_en2 register pme_sts2 register ri2 ri1 kbd mouse en_ri2 en_ri1 en_kbd en_mouse en_ring en_devint enable bit key to symbols npme pin pme_en pme_sts gp11 gp12 gp13 gp14 en_gp11 en_gp12 en_gp13 en_gp14 en_gp15 en_gp16 en_gp17 gp10 en_gp10 gp15 gp16 gp17 dev_int ring from smi/pme device interrupt block pme_en registers pme_sts registers sticky status bit: cleared by software writing a 1 to its bit location sci_en sci_en1 gpe_en.0 sci_sts1 gpe_sts.0 gpe_en register gpe_sts register nsci on irqx pin nsci on serial irqx bit[2] of irq mux control register irq9 bits[6:5] of irq mux control register nsci npme bit[5] mux bit[6] 0 0 0 1 1 0 wak_ctrl wak_sts npoweron pwrbtn_en pwrbtn_sts pm1_blk downloaded from: http:///
157 figure 8 - smi/pme logic configuration en_mint en_kint en_irint en_bint en_p12 smi_en1 register smi_sts1 register smi_en2 register smi_sts2 register smi_en registers smi_sts registers pint u2int u1int fint gpint1 wdt en_pint en_u2int en_u1int en_fint en_gpint2 en_gpint1 en_wdt mint kint irint bint p12 interrupt status bit: cleared at source enable bit key to symbols nsmi en_smi bit 7 of smi_en2 register out to pin or serial irq2 group smi dev_int to npme interface logic en_smi_pme bit 6 of smi_en2 register en_ring nring event pint u2int u1int fint gpint1 wdt mint kint irint bint p12 gpint2 gpint2 slp_ctrl bit 0 of the sleep enable configuration register 0xf0 of logical device a. slp_en_smi slp_en interrupt status bit: cleared by a read of register sticky status bit: cleared by a write of 1 to this bit ring bit, pme_sts1 register downloaded from: http:///
10 the configuration of t he fdc37b72x is very flexible and is based on the configuration architecture implemented in typical plug-and-play components. the fdc37b72x is designed for motherboard applications in which the resources required by their components are known. with its flexible resource alloca tion architecture, the fdc37b72x allows the bios to assign resources at post. system elements primary configuration address decoder after a hard reset (reset_drv pin asserted) or vcc power on reset the fdc37b72x is in the run mode with all logical devices disabled. the logical devices may be configured through two standard configuration i/o ports (index and data) by placing the fdc37b72x into configuration mode. the bios uses these configuration ports to init ialize the logical devices at post. the index and data ports are only valid when the fdc37b72x is in configuration mode. the sysopt pin is latched on the falling edge of the reset_drv or on vcc power on reset to determine the configurat ion register's base address. the sysopt pin is used to select the config port's i/o address at power-up. once powered up the configur ation port base address can be changed through c onfiguration registers cr26 and cr27. the sysopt pin is a hardware configuration pin which is shared with the nrts1 signal on pin 115. during reset this pin is a weak active low signal which sinks 30a. note: all i/o addresses are qualified with aen. the index and data ports are effective only when the chip is in t he configuration state. port name sysopt= 0 (pull-down resistor) refer to note 1 sysopt= 1 (10k pull-up resistor) type config port (note 2) 0x03f0 0x0370 write index port (note 2) 0x03f0 0x0370 read/write data port index port + 1 read/write note 1: if using ttl rs232 drivers use 1k pull-down. if using cmos rs232 drivers use 10k pull-down. note 2: the configuration port base addr ess can be relocated through cr26 and cr27. entering the configuration state the device enters the c onfiguration state when the following config key is successfully written to the config port. config key = < 0x55> when in configuration mode, all logical devices function properly. entering and exiting configuration mode has no effect on the devices. exiting the configuration state the device exits the conf iguration state when the following config key is successfully written to the config port. config key = < 0xaa> configuration sequence to program the configur ation registers, the following sequence must be followed: 1. enter configuration mode downloaded from: http:///
160 2. configure the conf iguration registers 3. exit confi guration mode. enter configuration mode to place the chip into the configuration state the config key is sent to the chip's config port. the config key consists of a write of 0x55 data to the config port. once the initiation key is received correctly the chip enters into the configuration state (t he auto config ports are enabled). configuration mode the system sets the logical device information and activates desired logical devices through the index and data ports. in configuration mode, the index port is loca ted at the config port address and the data port is at index port address + 1. the desired configurati on registers are accessed in two steps: a. write the index of t he logical device number configuration register (i.e., 0x07) to the index port and then writ e the number of the desired logical device to the data port b. write the address of the desired configuration register within the logi cal device to the index port and then write or read the configuration register through the data port. note: if accessing the global configuration registers, step (a) is not required. exit configuration mode to exit the configuration state the system writes 0xaa to the config port. the chip returns to the run state. note: only two states are defined (run and configuration). in the run state the chip will always be ready to enter the configurat ion state. downloaded from: http:///
161 programming example the following is an example of a configurat ion program in intel 8086 assembly language. ;--------------------------------------------------. ; enter configuration mode | ;--------------------------------------------------' mov dx,3f0h mov ax,055h cli ; disable interrupts out dx,al sti ; enable interrupts ;--------------------------------------------------. ; configure register cre0, | ; logical device 8 | ;--------------------------------------------------' mov dx,3f0h mov al,07h out dx,al ; point to ld# config reg mov dx,3f1h mov al, 08h out dx,al ; point to logical device 8 ; mov dx,3f0h mov al,e0h out dx,al ; point to cre0 mov dx,3f1h mov al,02h out dx,al ; update cre0 ;-------------------------------------------------. ; exit configuration mode | ;-------------------------------------------------' mov dx,3f0h mov ax,0aah out dx,al notes: 1. hard reset: reset_drv pin asserted 2. soft reset: bit 0 of configur ation control register set to one 3. all host accesses are blocked for 500s after vcc por (see power-up timing diagram) downloaded from: http:///
162 configuration registers index type hard reset vcc por vtr por vbat por soft reset configuration register global configuration registers 0x02 w 0x00 0x00 0x00 - - config control 0x03 r/w 0x03 0x03 0x03 - - index address 0x07 r/w 0x00 0x00 0x00 - 0x 00 logical device number 0x20 r 0x4c 0x4c 0x4c - 0x 4c device id - hard wired 0x21 r 0x00 0x00 0x00 - 0x00 device rev - hard wired 0x22 r/w 0x00 (note 0) 0x00 (note 0) 0x00 (note 0) - 0x00 (note 0) power control 0x23 r/w 0x00 0x00 0x00 - - power mgmt 0x24 r/w 0x04 0x04 0x04 - - osc 0x26 r/w sysopt=0: 0xf0 sysopt=1: 0x70 sysopt=0: 0xf0 sysopt=1: 0x70 - - - configuration port address byte 0 0x27 r/w sysopt=0: 0x03 sysopt=1: 0x03 sysopt=0: 0x03 sysopt=1: 0x03 - - - configuration port address byte 1 0x28 r/w 0x00 0x00 - - 0x 00 clock mask register 0x2b r/w - 0x00 0x00 - - test 4 0x2c r/w - 0x00 0x00 - - test 5 0x2d r/w - 0x00 0x00 - - test 1 0x2e r/w - 0x00 0x00 - - test 2 0x2f r/w - 0x00 0x00 - - test 3 logical device 0 configuration registers (fdd) 0x30 r/w 0x00 0x00 0x00 - 0x00 activate 0x60, 0x61 r/w 0x03, 0xf0 0x03, 0xf0 0x03, 0xf0 - 0x03, 0xf0 primary base i/o address 0x70 r/w 0x06 0x06 0x06 - 0x06 primary interrupt select 0x74 r/w 0x02 0x02 0x02 - 0x02 dma channel select 0xf0 r/w 0x0e 0x0e 0x0e - - fdd mode register 0xf1 r/w 0x00 0x00 0x00 - - fdd option register 0xf2 r/w 0xff 0xff 0xff - - fdd type register 0xf4 r/w 0x00 0x00 0x00 - - fdd0 0xf5 r/w 0x00 0x00 0x00 - - fdd1 logical device 1 configuration registers (reserved) logical device 2 configuration registers (reserved) logical device 3 configuration registers (parallel port) 0x30 r/w 0x00 0x00 0x00 - 0x00 activate downloaded from: http:///
163 index type hard reset vcc por vtr por vbat por soft reset configuration register 0x60, 0x61 r/w 0x00, 0x00 0x00, 0x00 0x00, 0x00 - 0x00, 0x00 primary base i/o address 0x70 r/w 0x00 0x00 0x00 - 0x00 primary interrupt select 0x74 r/w 0x04 0x04 0x04 - 0x04 dma channel select 0xf0 r/w 0x3c 0x3c 0x3c - - parallel port mode register 0xf1 r/w 0x00 0x00 0x00 - - parallel port mode register 2 logical device 4 configuration registers (serial port 1) 0x30 r/w 0x00 0x00 0x00 - 0x00 activate 0x60, 0x61 r/w 0x00, 0x00 0x00, 0x00 0x00, 0x00 - 0x00, 0x00 primary base i/o address 0x70 r/w 0x00 0x00 0x00 - 0x00 primary interrupt select 0xf0 r/w 0x00 0x00 0x00 - - serial port 1 mode register logical device 5 configuration registers (serial port 2) 0x30 r/w - - 0x00 - - activate 0x60, 0x61 r/w 0x00, 0x00 0x00, 0x00 0x00, 0x00 - 0x00, 0x00 primary base i/o address 0x70 r/w 0x00 0x00 0x00 - 0x00 primary interrupt select 0xf0 r/w 0x00 0x00 0x00 - - serial port 2 mode register 0xf1 r/w 0x02 0x02 0x02 - - ir options register 0xf2 r/w 0x03 0x03 0x03 - - ir half duplex timeout logical device 6 configuration registers (reserved) logical device 7 configuration registers (keyboard) 0x30 r/w 0x00 0x00 0x00 - 0x00 activate 0x70 r/w 0x00 0x00 0x00 - 0x00 primary interrupt select 0x72 r/w 0x00 0x00 0x00 - 0x00 second interrupt select 0xf0 r/w 0x00 0x00 0x00 - - kreset and gatea20 select logical device 8 configuration registers (aux i/o) 0x30 r/w 0x00 0x00 0x00 - 0x00 activate 0xb0 r/w - - - 0x00 - soft power enable register 1 3 0xb1 r/w - - - 0x80 - soft power enable register 2 3 0xb2 r/w - - - 0x00 - soft power status register 1 3 0xb3 r/w - - - 0x00 - soft power status register 2 3 0xb8 r/w - - - 0x00 - delay 2 time set register 0xc0 r/w 0x00 0x00 - - - irq mux control 3 downloaded from: http:///
164 index type hard reset vcc por vtr por vbat por soft reset configuration register 0xc1 r/w 0x01 0x01 - - - force disk change 0xc2 r - - - - - floppy data rate select shadow 0xc3 r - - - - - uart1 fifo control shadow 0xc4 r - - - - - uart2 fifo control shadow 0xc5 r/w 0x00 0x00 - - - fdc forced write protect 0xc6 r/w - - - 0x00 - ring filter select 3 0xc8 r/w - - - 0x01 - gp50 3 0xca r/w - - - 0x09 - gp52 3 0xcb r/w - - - 0x01 - gp53 3 0xcc r/w - - - 0x01 - gp54 3 0xd0 r/w - - - 0x01 - gp60 3 0xd1 r/w - - - 0x01 - gp61 3 0xd2 r/w - - - 0x01 - gp62 3 0xd3 r/w - - - 0x01 - gp63 3 0xd4 r/w - - - 0x01 - gp64 3 0xd5 r/w - - - 0x01 - gp65 3 0xd6 r/w - - - 0x01 - gp66 3 0xd7 r/w - - - 0x01 - gp67 3 0xe0 r/w - - - 0x01 - gp10 3 0xe1 r/w - - - 0x01 - gp11 3 0xe2 r/w - - - 0x01 - gp12 3 0xe3 r/w - - - 0x01 - gp13 3 0xe4 r/w - - - 0x01 - gp14 3 0xe5 r/w - - - 0x01 - gp15 3 0xe6 r/w - - - 0x01 - gp16 3 0xe7 r/w - - - 0x01 - gp17 3 0xef r/w - - - 0x00 - gp_int2 3 0xf0 r/w - - - 0x00 - gp_int1 3 0xf1 r/w 0x00 0x00 0x00 - - wdt_units 0xf2 r/w 0x00 0x00 0x00 - - wdt_val 0xf3 r/w 0x00 0x00 0x00 - - wdt_cfg 0xf4 r/w (1) note 5 note 5 0x00 - - wdt_ctrl 0xf6 r/w - - - 0x00 - gp1 3 0xf9 r/w - - - 0x00 - gp5 3 0xfa r/w - - - 0x00 - gp6 3 downloaded from: http:///
165 index type hard reset vcc por vtr por vbat por soft reset configuration register logical device a configuration registers (acpi) 0x30 r/w 0x00 0x00 0x00 - 0x00 activate 4 0x60, 0x61 (2) r/w 0x00, 0x00 0x00, 0x00 0x00, 0x00 - 0x00, 0x00 primary base i/o address pm1_blk 0x70 r/w - - - 0x00 - primary interrupt select 3 0xf0 r/w - - - 0x00 - sleep/wake configuration 3 notes note 0: cr22 bit 5 is reset on vtr por only note 1: this register contains some bits which are read or write only. note 2: register 60 is the high byte; 61 is the low byte. for example to set the primary base address to 1234h, write 12h into 60, and 34h into 61. note 3: these configuration registers are powered by vtr and battery backed up. note 4: the activate bit for logical device a does not effect the generation of an interrupt (sci). note 5: bits[0,2-7] are cleared on a v cc por or reset_drv. downloaded from: http:///
166 chip level (global) control/configuration registers [0x00-0x2f] the chip-level (global) registers lie in the address range [0x00-0x2f]. the design must use all 8 bits of the address port for register select ion. all unimplemented registers and bits ignore writes and return zero when read. the index port is used to select a configuration register in the chip. the data port is then used to access the selected register. these registers are accessible only in the configuration mode. table 63 - chip level registers register address description state chip (global) control registers 0x00 - 0x01 reserved - writes are ignored, reads return 0. config control default = 0x00 on vcc por or reset_drv 0x02 w the hardware automatically clears this bit after the write, there is no need for software to clear the bits. bit 0 = 1: soft reset. refer to the "configuration registers" table for the soft reset value for each register. c index address default = 0x03 on vcc por or reset_drv 0x03 r/w bit[7] = 1 enable gp1, wdt_ctrl, gp5, gp6, soft power enable and status register access when not in configuration mode = 0 disable gp1, wdt_ctrl, gp5, gp6, soft power enable and status register access when not in configuration mode (default) bits [6:2] reserved - writes are ignored, reads return 0. bits[1:0] sets gp1 etc. selection r egister used when in run mode (not in configuration mode). = 11 0xea (default) = 10 0xe4 = 01 0xe2 = 00 0xe0 0x04 - 0x06 reserved - writes are ignored, reads return 0 . logical device # default = 0x00 on vcc por or reset_drv 0x07 r/w a write to this register se lects the current logical device. this allows access to the control and configuration registers for each logical device. note: the activate command operates only on the selected logical device. c card level reserved 0x08 - 0x1f reserved - writes are ignored, reads return 0 . chip level, smsc defined downloaded from: http:///
167 register address description state device id hard wired = 0x4c 0x20 r a read only register which provides device i dentification. bits[7:0] = 0x4c when read c device rev hard wired = 0x00 0x21 r a read only register which provides device revision information. bits[7:0] = 0x00 when read c powercontrol default = 0x00. on vcc por or reset_drv hardware signal. 0x22 r/w bit[0] fdc power bit[1] reserved bit[2] reserved bit[3] parallel port power bit[4] serial port 1 power bit[5] serial port 2 power bit[6] reserved bit[7] reserved = 0 power off or disabled = 1 power on or enabled c power mgmt default = 0x00. on vcc por or reset_drv hardware signal 0x23 r/w bit[0] fdc bit[1] reserved bit[2] reserved bit[3] parallel port bit[4] serial port 1 bit[5] serial port 2 bit[6] reserved (read as 0) bit[7] reserved (read as 0) = 0 intelligent pwr mgmt off = 1 intelligent pwr mgmt on c osc default = 0x04, on vcc por or reset_drv hardware signal. 0x24 r/w bit[0] reserved bit [1] pll control = 0 pll is on (backward compatible) = 1 pll is off bits[3:2] osc = 01 osc is on, brg clock is on. = 10 same as above (01) case. = 00 osc is on, brg clock enabled. = 11 osc is off, brg clock is disabled. bit [6:4] reserved , set to zero bit[7] irq8 polarity = 0 irq8 is active high = 1 irq8 is active low c chip level vendor defined 0x25 reserved - writes are ignored, reads return 0. downloaded from: http:///
168 register address description state configuration address byte 0 default=0xf0 (sysopt=0) =0x70 (sysopt=1) on vcc por or reset_drv 0x26 bit[7:1] configuration address bits [7:1] bit[0] = 0 see note 1 below c configuration address byte 1 default = 0x03 on vcc por or reset_drv 0x27 bit[7:0] configuration address bits [15:8] see note 1 below c chip level vendor defined 0x28 -0x2a reserved - writes are ignored, reads return 0. test 4 0x2b r/w test modes: reserv ed for smsc. users should not write to this register, may produce undesired results. c test 5 0x2c r/w test modes: reserv ed for smsc. users should not write to this register, may produce undesired results. c test 1 0x2d r/w test modes: reserv ed for smsc. users should not write to this register, may produce undesired results. c test 2 0x2e r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. c test 3 default = 0x00, on vcc por or reset_drv hardware signal. 0x2f r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. c note 1: to allow the selection of the configuration address to a user def ined location, these configuration address bytes are used. there is no restriction on the address chosen, except that a0 is 0, that is, the address must be on an even byte boundary. as soon as both by tes are changed, the configuration space is moved to t he specified location with no delay (note: write byte 0, then byte 1; writing cr27 changes the base address). the configuration address is only reset to its default address upon a hard reset or vcc por. note: the default configuration address is either 3f0 or 370, as specified by the sysopt pin. this change affects smsc mode only. downloaded from: http:///
169 logical device configuration/control registers [0x30-0xff] used to access the registers that are assigned to each logical unit. this chip supports seven logical units and has seven sets of logical device registers. the logical devices are floppy, parallel port, serial port 1 and serial port 2, keyboard controller, auxiliary i/o and acpi. a separate set (bank) of control and confi guration register exists for each logical device and is selected with the logical device # register (0x07). the index port is used to select a specific logical device register. these registers are then accessed through the data port. the logical device registers are accessible only when the device is in the configuration state. the logical register addresses are: logical device registers table 64 - logical device registers logical device register address description state activate note1 default = 0x00 on vcc por or reset_drv note 2 (0x30) bits[7:1] re served, set to zero. bit[0] = 1 activates the logical device currently selected through the logical device # register. = 0 logical device currently selected is inactive c logical device control (0x31-0x37) reserved - writes are ignored, reads return 0. c logical device control (0x38-0x3f) vendor de fined - reserved - writes are ignored, reads return 0. c mem base addr (0x40-0x5f) reserved - writes are ignored, reads return 0. c i/o base addr. (see device base i/o address table) default = 0x00 on vcc por or reset_drv (0x60-0x6f) 0x60,2,... = addr[15:8] 0x61,3,... = addr[7:0] registers 0x60 and 0x61 set the base address for the device. if more than one base address is required, the second base address is set by registers 0x62 and 0x63. refer to - i/o base address configuration register description - for the number of base address registers used by each device. unused registers will ignore writes and return zero when read. c interrupt select defaults : 0x70 = 0x00, on vcc por or reset_drv 0x72 = 0x00, on vcc por or reset_drv (0x70,072) 0x70 is implemented for each logical device. refer to interrupt configuration regist er description. only the keyboard controller uses in terrupt select register 0x72. unused register (0 x72) will ignore writes and return zero when read. interrupts default to edge high (isa compatible). c downloaded from: http:///
170 logical device register address description state (0x71,0x73) reserved - not implemented. these register locations ignore writes and return zero when read. dma channel select default = 0x04 on vcc por or reset_drv (0x74,0x75) only 0x74 is implem ented for fdc, serial port 2 and parallel port. 0x75 is not implemented and ignores writes and returns zero when read. refer to dma channel configuration. c 32-bit memory space configuration (0x76-0xa8) reserved - not im plemented. these register locations ignore writes and return zero when read. logical device (0xa9-0xdf) reserved - not implemented. these register locations ignore writes and return zero when read. c logical device config. (0xe0-0xfe) reserved - vendor defined (see smsc defined logical device configuration registers) c reserved 0xff reserved c note 1: a logical device will be active and powered up according to the following equation: device on (active) = (activate bit set or pwr/control bit set). the logical device's activate bit and its pwr/c ontrol bit are linked such that setting or clearing one sets or clears the other. note: if the i/o base addr of the logical device is not within the base i/o range as shown in the logical device i/o map, then read or wr ite is not valid and is ignored. note 2. the activate bit fo r logical device 5 (serial port 2) is reset on vtr por only. downloaded from: http:///
171 i/o base address configuration register table 65 - i/o base address configuration register description logical device number logical device register index base i/o range (note3) fixed base offsets 0x00 fdc (note 4) 0x60,0x61 [0x100:0x0ff8] on 8 byte boundaries +0 : sra +1 : srb +2 : dor +3 : tsr +4 : msr/dsr +5 : fifo +7 : dir/ccr 0x03 parallel port 0x60,0x61 [0x100:0x0ffc] on 4 byte boundaries (epp not supported) or [0x100:0x0ff8] on 8 byte boundaries (all modes supported, epp is only available when the base address is on an 8-byte boundary) +0 : data|ecpafifo +1 : status +2 : control +3 : epp address +4 : epp data 0 +5 : epp data 1 +6 : epp data 2 +7 : epp data 3 +400h : cfifo|ecpdfifo|tfifo |cnfga +401h : cnfgb +402h : ecr 0x04 serial port 1 0x 60,0x61 [0x100:0x0ff8] on 8 byte boundaries +0 : rb/tb|lsb div +1 : ier|msb div +2 : iir/fcr +3 : lcr +4 : msr +5 : lsr +6 : msr +7 : scr 0x05 serial port 2 0x 60,0x61 [0x100:0x0ff8] on 8 byte boundaries +0 : rb/tb|lsb div +1 : ier|msb div +2 : iir/fcr +3 : lcr +4 : msr +5 : lsr +6 : msr +7 : scr 0x07 kybd n/a not relocatable fixed base address: 60,64 +0 : data register +4 : command/status reg. 0x08 aux i/o n/a not relocatable n/a downloaded from: http:///
172 logical device number logical device register index base i/o range (note3) fixed base offsets 0x0a acpi 0x60,0x 61 [0x00:0x0fe7] on 24 byte boundaries note 3: this chip uses isa address bits [a11:a0] to decode the base address of each of its logical devices. interrupt select configuration register table 66 - interrupt select configuration register description name reg index definition state interrupt request level select 0 default = 0x00 on vcc por or reset_drv 0x70 (r/w) bits[3:0] selects whic h interrupt level is used for interrupt 0. 0x00=no interrupt selected. 0x01=irq1 0x02=irq2 0x0e=irq14 0x0f=irq15 note: all interrupts are edge high (except ecp/epp) c note: an interrupt is activated by setting the interrupt request level se lect 0 register to a non-zero value and : for the fdc logical device by setting dmaen, bit d3 of the digital output register. for the pp logical device by setti ng irqe, bit d4 of the control port and in addition for the pp logical device in ecp mo de by clearing serviceint r, bit d2 of the ecr. for the serial po rt logical device by setting any combination of bits d0-d3 in the ier and by setting the out2 bit in the uart's modem control (mcr) register. for the kybd by (refer to the kybd controller section of this spec.) note: irq pins must tri-state if not used/selected by any logical device. refer to note a. downloaded from: http:///
173 dma channel select configuration register table 67 - dma channel select configuration register description name reg index definition state dma channel select default = 0x04 on vcc por or reset_drv 0x74 (r/w) bits[2:0] select the dma channel. 0x00=dma0 0x01=dma1 0x02=dma2 0x03=dma3 0x04-0x07= no dma active c note: a dma channel is activated by setting the dm a channel select register to [0x00-0x03] and : for the fdc logical device by setting dmaen, bit d3 of the digital output register. for the pp logical device in ecp mode by setting dmaen, bit d3 of the ecr. for the uart 2 logical device, by setting the dma enable bit. refer to the ircc specification. note: dmareq pins must tri-stat e if not used/selected by any lo gical device. refer to note a. downloaded from: http:///
174 note a. logical device irq and dma operation 1) irq and dma enable and disable: any time the irq or dack for a logical block is disabled by a register bit in that logical blo ck, the irq and/or dack must be dis abled. this is in addition to the irq and dack disabled by the configuration r egisters (active bit or address not valid). 2) fdc: for the following cases, the irq and dack used by the fdc are disabled (high impedance). will not respond to the dreq (a) digital output register (bas e+2) bit d3 (dmaen) set to "0". (b) the fdc is in power down (disabled). 3) serial port 1 and 2: modem cont rol register (mcr) bit d2 (out2) - when out2 is a logic "0", the serial port interrupt is forced to a high impedance state - disabled. 4) parallel port: spp and epp modes: control port (base+ 2) bit d4 (irqe) set to "0", irq is disabled (high impedance). 1) ecp mode: (a) (dma) dmaen from ecr register. see table. (b) irq - see table. mode (from ecr register) irq pin controlled by pdreq pin controlled by 000 printer irqe dmaen 001 spp irqe dmaen 010 fifo (on) dmaen 011 ecp (on) dmaen 100 epp irqe dmaen 101 res irqe dmaen 110 test (on) dmaen 111 config irqe dmaen 1) keyboard controller: refer to the kbd section of this spec. downloaded from: http:///
175 smsc defined logical device configuration registers the smsc specific logical device c onfiguration registers reset to thei r default values only on hard resets generated by vcc por or vtr por or vbat por (a s shown) or the reset_drv signal. these registers are not affected by soft resets. table 68 - floppy disk controller, logical device 0 [logical device number = 0x00] name reg index definition state fdd mode register default = 0x0e on vcc por or reset_drv 0xf0 r/w bit[0] floppy mode = 0 normal floppy mode (default) = 1 enhanced floppy mode 2 (os2) bit[1] fdc dma mode = 0 burst mode is enabled = 1 non-burst mode (default) bit[3:2] interface mode = 11 at mode (default) = 10 (reserved) = 01 ps/2 = 00 model 30 bit[4] swap drives 0,1 mode = 0 no swap (default) = 1 drive and motor sel 0 and 1 are swapped. bits[5] reserved, set to zero. bit [6] output type control: 0= fdc outputs are od24 open drain (default) 1= fdc outputs are o24 push-pull. bit [7] fdc output control: 0= fdc outputs active (default) 1= fdc outputs tristated note: these bits do not affect the parallel port fdc pins. c fdd option register default = 0x00 on vcc por or reset_drv 0xf1 r/w bits[1:0] re served, set to zero bits[3:2] density select = 00 normal (default) = 01 normal (reserved for users) = 10 1 (forced to logic "1") = 11 0 (forced to logic "0") bit[5:4] reserved, set to zero bits[7:6] boot floppy = 00 fdd 0 (default) = 01 fdd 1 = 10 reserved (neither drive a or b is a boot drive). = 11 reserved (neither drive a or b is a boot drive). c downloaded from: http:///
176 name reg index definition state fdd type register default = 0xff on vcc por or reset_drv 0xf2 r/w bits[1:0] floppy drive a type bits[3:2] floppy drive b type bits[5:4] reserved (could be used to store floppy drive c type) bits[7:6] reserved (could be used to store floppy drive d type) note: the fdc37b72x supports two floppy drives c 0xf3 r reserved, read as 0 (read only) c fdd0 default = 0x00 on vcc por or reset_drv 0xf4 r/w bits[1:0] drive type select: dt1, dt0 bits[2] read as 0 (read only) bits[4:3] data rate table select: drt1, drt0 bits[5] read as 0 (read only) bits[6] precompensation disable pts =0 use precompensation =1 no precompensation bits[7] read as 0 (read only) c fdd1 0xf5 r/w refer to def inition and default for 0xf4 c downloaded from: http:///
177 parallel port, logical device 3 table 69 - parallel port, logical de vice 3 [logical device number = 0x03] name reg index definition state pp mode register default = 0x3c on vcc por or reset_drv 0xf0 r/w bits[2:0] parallel port mode = 100 printer mode (default) = 000 standard and bi-directional (spp) mode = 001 epp-1.9 and spp mode = 101 epp-1.7 and spp mode = 010 ecp mode = 011 ecp and epp-1.9 mode = 111 ecp and epp-1.7 mode bit[6:3] ecp fifo threshold 0111b (default) bit[7] pp interrupt type not valid when the parallel port is in the printer mode (100) or the standard & bi-directional mode (000). = 1 pulsed low, released to high-z. = 0 irq follows nack when parallel port in epp mode or [printer,spp, epp] under ecp. irq level type when the parallel port is in ecp, test, or centronics fifo mode. c pp mode register 2 default = 0x00 on vcc por or reset_drv 0xf1 r/w bits[1:0] ppfdc - muxed pp/fdc control = 00 normal parallel port mode = 01 ppfd1: drive 0 is on the fdc pins drive 1 is on the parallel port pins drive 2 is on the fdc pins drive 3 is on the fdc pins = 10 ppfd2: drive 0 is on the parallel port pins drive 1 is on the parallel port pins drive 2 is on the fdc pins drive 3 is on the fdc pins bits[7:2] reserved . set to zero. downloaded from: http:///
178 serial port 1, logical device 4 table 70 - serial port 1, logical device 4 [logical device number = 0x04] name reg index definition state serial port 1 mode register default = 0x00 on vcc por or reset_drv 0xf0 r/w bit[0] midi mode = 0 midi support disabled (default) = 1 midi support enabled bit[1] high speed = 0 high speed disabled(default) = 1 high speed enabled bit[6:2] reserved, set to zero bit[7]: share irq =0 uarts use different irqs =1 uarts share a common irq see note 1 below. c note 1: to properly share and irq, 1. configure uart1 (or uart2) to use the desired irq pin. 2. configure uart2 (or uart1) to use no irq selected. 3. set the share irq bit. note: if both uarts are configured to use different irq pins and the share irq bit is set, then both of the uart irq pins will assert when ei ther uart generates an interrupt. downloaded from: http:///
179 serial port 2, logical device 5 table 71 - serial port 2, logical device 5 [logical device number = 0x05] name reg index definition state serial port 2 mode register default = 0x00 on vcc por or reset_drv 0xf0 r/w bit[0] midi mode = 0 midi support disabled (default) = 1 midi support enabled bit[1] high speed = 0 high speed disabled(default) = 1 high speed enabled bit[7:2] reserved, set to zero c ir option register default = 0x02 on vcc por or reset_drv 0xf1 r/w bit[0] re ceive polarity = 0 active high (default) = 1 active low bit[1] transmit polarity = 0 active high = 1 active low (default) bit[2] duplex select = 0 full duplex (default) = 1 half duplex bits[5:3] ir mode = 000 standard (default) = 001 irda = 010 ask-ir = 011 reserved = 1xx reserved bit[6] ir location mux = 0 use serial port txd2 and rxd2 (default) = 1 use alternate irrx2 (pin 81) and irtx2 (pin 82) bit[7] reserved, write 0 c ir half duplex timeout default = 0x03 on vcc por or reset_drv 0xf2 bits [7:0] these bits set the half duplex time-out for the ir port. this value is 0 to 10msec in 100usec increments. 0= blank during transmit/receive 1= blank during transmit/receive + 100usec . . . downloaded from: http:///
180 kybd, logical device 7 table 72 - kybd, logical device 7 [logical device number = 0x07] name reg index definition state krst_ga20 default = 0x00 on vcc por or reset_drv 0xf0 r/w kreset and gatea20 select bit[7] polarity select for p12 = 0 p12 active low (default) = 1 p12 active high bits[6:3] reserved bit[2] port 92 select = 0 port 92 disabled = 1 port 92 enabled bit[1] gatea20 select = 0 software control = 1 hardware speed-up bit[0] kreset select = 0 software control = 1 hardware speed-up 0xf1 - 0xff reserved - read as 0 downloaded from: http:///
181 auxiliary i/o, logical device 8 table 73 - auxiliary i/o, logical device 8 [logical device number = 0x08] name reg index definition state soft power enable register 1 default = 0x00 on vbat por 0xb0 r/w the following bits are the enables for the wake-up function of the npoweron bit. when enabled, these bits allow their corresponding function to turn on power to the system. 1 = enabled 0 = disabled bit[0] sp_ri1: uart 1 ring indicator pin bit[1] sp_ri2: uart 2 ring indicator pin bit[2] sp_kdat: keyboard data pin bit[3] sp_mdat: mouse data pin bit[4] sp_gpint1: group interrupt 1 bit[5] sp_gpint2: group interrupt 2 bit[6] sp_irrx2: irrx2 input pin bit[7] reserved c soft power enable register 2 default = 0x80 on vbat por 0xb1 r/w the following bits are the enables for the wake-up function of the npoweron bit. when enabled, these bits allow their corresponding function to turn on power to the system. 1 = enabled 0 = disabled bit[0] sp_rxd1: uart 1 receive data pin bit[1] sp_rxd2: uart 2 receive data pin bit[2] reserved bit[3] ring enable bit ring_en 1=enable ring indicator on nring pin as wakeup function to activate npoweron. 0=disable. bit[4] vtr_por_off. controls state of npoweron after vtr por. 1=the npoweron pin will go inactive (float) and the machine will remain off when the vtr por occurs. software must not set vtr_por_off and vtr_por_en at the same time. 0=the npoweron pin will remain in the state it was in prior to the vtr por (unless the vtr_por_en bit is set). bit[5] reserved bit[6] vtr_por_en. controls state of npoweron after vtr por. 1= the npoweron pin will go active (low) and the c downloaded from: http:///
182 name reg index definition state machine will power-up as soon as a vtr por occurs. software must not set vtr_por_off and vtr_por_en at the same time. 0=the npoweron pin will remain in the state it was in prior to the vtr por (unless the vtr_por_off bit is set). bit[7] off_en: after power up, this bit defaults to 1, i.e., enabled. this bit allows the software to enable or disable the button control of power off. soft power status register 1 default = 0x00 on vbat por 0xb2 r/w the following bits are the status for the wake-up function of the npoweron bit. these indicate which of the enabled wakeup func tions caused the power up. 1 = occurred 0 = did not occur since last cleared the following signals are latched to detect and hold the soft power event (type 1) (note 1) bit[0] ri1: uart 1 ring indicator; high to low transition on the pin, cleared by a read of this register bit[1] ri2: uart 2 ring indicator; high to low transition on the pin, cleared by a read of this register bit[2] kdat: keyboard data; high to low transition on the pin, cleared by a read of this register bit[3] mdat: mouse data; high to low transition on the pin, cleared by a r ead of this register bit[6] irrx2: irrx2 input; high to low transition on the pin, cleared by a r ead of this register bit[7] reserved the following signals are not latched to detect and hold the soft power event (type 2) (note 1) bit[4] gpint1: group interrupt 1; status of the gpint1 internal signal. cleared at the source bit[5] gpint2: group interrupt 2; status of the gpint2 internal signal. cleared at the source c soft power status register 2 default = 0x00 on vbat por 0xb3 r/w the following bits are the status for the wake-up function of the npoweron bit. these indicate which of the enabled wak eup functions caused the power up. 1 = occurred 0 = did not occur since last cleared c downloaded from: http:///
183 name reg index definition state the following signals are latched to detect and hold the soft power event (type 1) (note 1) bit[0] rxd1: uart 1 rece ive data; high to low transition on the pin, cleared by a read of this register bit[1] rxd2: uart 2 rece ive data; high to low transition on the pin, cleared by a read of this register bit[3] ring status bit r ing_sts; latched, cleared on read. 0= nring input did not occur. 1= ring indicator input occurred on the nring pin and, if enabled, caused the wakeup (activated npoweron) bit[5:4] reserved the following signal is latched to detect and hold the soft power event (type 3) (note 1) but the output of the latch does not feed into the power down circuitry: bit[2] button: button press ed, cleared by a read of this register bits[7:6] reserved delay 2 time set register default = 0x00 on vtr por 0xb8 r/w this register is used to set delay 2 (for soft power management) to a value from 500 msec to 32 sec. the default value is 500msec. engineering note: this delay is started if off_en is enabled and off_dly was set and a button input comes in. bits[5:0] the value of these bits correspond to the delay time as follows: 000000= 500msec min to 510msec max 000001= 1sec min to 1.01sec max 000010= 1.5sec min to 1.51sec max 000011= 2sec min to 2.01sec max ... 111111 = 32sec min to 32.01sec max bits[7:6] reserved c irq mux control register default = 0x00 on vbat por 0xc0 r/w this register is used to configure the irqs, including pme, sci and smi. bit[0] serial/parallel irqs 0=serial irqs are used 1=parallel irqs are used note 1: this bit does not control the sci or smi downloaded from: http:///
184 name reg index definition state interrupts. see bits 2,7 of this register. note 2: if set, the bios buffe r is disabled. also, the ser_irq and pci_clk pins are disabled, and these pins function as irq15 and irq14, respectively. note 3: select irq9 below . select sci below. select nsmi through the smi register. bit[1] reserved bit[2] sci select 0=sci is on serial irq frame 1=sci is on irqx pin bit[3] sci polarity select (en1) 0=sci active low 1=sci active high bit[4] sci buffer type (en1) 0=push-pull 1=open drain bit[6:5] sci/pme/ir q9 pin select 00=pin 21 is used for pme# signal. 01=pin 21 is used for sci. 10=pin 21 is used for irq9. 11=reserved note: if bit 5 is set, this overrides the setting of the irq for sci in config register 0x70 of logical device a. see the logic in the sci section. note: this bit selects the buffer type of the pin as follows: if pme#is selected, it is active low od; if sci is selected, the buffer ty pe and polarity are selected through bits 3 and 4 of this register; if irq9 is selected, it is an active high push-pull output. bit[7] smi select 0=smi is on serial irq frame (irq2) 1=smi is on nsmi pin engineering note: the polarity and buffer type of the smi pin is selected through the gpio registers (default is active low open drain). forced disk change default = 0x03 on vtr por 0xc1 r/w force change 1 and force change 0 can be written to 1 are not clearable by software. force change 1 is cleared on (nstep and nds1) force change 0 is cleared on (nstep and nds0). dsk chg (floppy dir register, bit 7) = (nds0 and force change 0) or (nds1 and force change 1) or ndskchg. setting either of the force disk change bits active (1) forces the fdd ndskchg input active when downloaded from: http:///
185 name reg index definition state the appropriate drive has been selected. bit[0] force change for fdc0 0=inactive 1=active bit[1] force change for fdc1 0=inactive 1=active bit[2:7] reserved, reads 0 floppy data rate select shadow 0xc2 r floppy data rate select shadow register bit[7] soft reset bit[6] power down bit[5] reserved bit[4] precomp 2 bit[3] precomp 1 bit[2] precomp 0 bit[1] data rate select 1 bit[0] data rate select 0 uart1 fifo control shadow 0xc3 r uart1 fifo control shadow register bit[7] rcvr trigger msb bit[6] rcvr trigger lsb bit[5] reserved bit[4] reserved bit[3] dma mode select bit[2] xmit fifo reset bit[1] rcvr fifo reset bit[0] fifo enable uart2 fifo control shadow 0xc4 r uart2 fifo control shadow register bit[7] rcvr trigger msb bit[6] rcvr trigger lsb bit[5] reserved bit[4] reserved bit[3] dma mode select bit[2] xmit fifo reset bit[1] rcvr fifo reset bit[0] fifo enable forced write protect default = 0x00 on vtr por 0xc5 r/w force write protec t function forces the fdd nwrtprt input active if the force wrtprt bit is active. the force write protect function applies to the nwrtprt pin in the fdd interface as well as the nwrtprt pin in the parallel port fdc. bit[0] force write protect bit fdd0 0 = inactive (default) 1 = active forces the fdd nwrtprt input active when the drive has been selected note 2 bit[1:7] reserved, reads 0. ring filter select 0xc6 r/w this register is used to select the operation of the c downloaded from: http:///
186 name reg index definition state register default = 0x00 on vbat por note 3 ring indicator on the nri1, nri2 and nring pins. it also contains bits to select crystal load capacitance and p17/p12 function. bit[0]: 1=enable detection of pulse train of frequency 15hz or higher for 200msec and generate an active low pulse for its duration to use as the ring indicator function on nring pin. the leading high-to-low edge is the trigger for the ring indication. 0=ring indicate function is high-to-low transition on the nring pin. bit[1]: 1=enable detection of pulse train of frequency 15hz or higher and generate an active low pulse for its duration to use for 200msec as the ring indicator function on nri1 pin. the leading high-to-low edge is the trigger for the ring indication. 0=ring indicate function is high-to-low transition on the nri1 pin. bit[2]: 1=enable detection of pulse train of frequency 15hz or higher and generate an active low pulse for its duration to use for 200msec as the ring indicator function on nri2 pin. the leading high-to-low edge is the trigger for the ring indication. 0=ring indicate function is high-to-low transition on the nri2 pin. bit[5:3] reserved bit[6] xtal cap. this bit is used to specify the load capacitance of t he 32khz xtal: 0=12pf (default), 1=6pf. bit[7] p17/p12. 0=the f unction of p17/p12 on gp12 (pin 79) and gp64 (pin 87) is p17. (default) 1=the function of p17/ p12 on gp12 (pin 79) and gp64 (pin 87) is p12 and the keylock function is not active. downloaded from: http:///
187 table 74 - auxiliary i/o, logical device 8 [logical device number = 0x08] name reg index definition state gp10 default = 0x01 on vbat por 0xe0 general purpose i/0 bit 1.0 bit[0] in/out : =1 in put, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] group interrupt enable =1 enable combined irq 1 =0 disable combined irq 1 bit[3] function select =1 nsmi =0 gpi/o bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull c gp11 default = 0x01 on vbat por 0xe1 general purpose i/0 bit 1.1 bit[0] in/out : =1 in put, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] group interrupt enable =1 enable combined irq 1 =0 disable combined irq 1 bit[4:3] function select =00 gpi/o =01 nring =10 either edge triggered interrupt 1 =11 reserved bits[6:5] reserved bit[7] output type select 1=open drain 0=push pull c gp12 default = 0x01 on vbat por 0xe2 general purpose i/0 bit 1.2 bit[0] in/out : =1 in put, =0 output bit[1] polarity :=1 invert, =0 no invert bit[2] group interrupt enable =1 enable combined irq 1 =0 disable combined irq 1 bit[4:3] function select =00 gpi/o =01 wdt =10 p17/p12 1 =11 either edge triggered interupt 2 bits[6:5] reserved bit[7] output type select 1=open drain 0=push pull note 1: this function is se lected via bit 7 of the ring filter select register. default is p17. c downloaded from: http:///
188 name reg index definition state gp13 default = 0x01 on vbat por 0xe3 general purpose i/0 bit 1.3 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] group interrupt enable =1 enable combined irq 1 =0 disable combined irq 1 bit[3] function select =1 led =0 gpi/o bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull c gp14 default = 0x01 on vbat por 0xe4 general purpose i/0 bit 1.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] group interrupt enable =1 enable combined irq 1 =0 disable combined irq 1 bit[3] function select =1 irrx2 =0 gpi/o bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull c gp15 default = 0x01 on vbat por 0xe5 general purpose i/0 bit 1.5 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] group interrupt enable =1 enable combined irq 1 =0 disable combined irq 1 bit[3] function select =1 irtx2 =0 gpi/o bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull c gp16 default = 0x01 on vbat por 0xe6 general purpose i/0 bit 1.6 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] group interrupt enable =1 enable combined irq 1 =0 disable combined irq 1 bit[3] function select c downloaded from: http:///
189 name reg index definition state =1 nmtr1 =0 gpi/o bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull gp17 default = 0x01 on vbat por 0xe7 general purpose i/0 bit 1.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] group interrupt enable =1 enable combined irq 1 =0 disable combined irq 1 bit[3] function select =1 nds1 =0 gpi/o bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull c gp50 default = 0x01 on vbat por 0xc8 general purpose i/0 bit 5.0 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] reserved bit[4:3] function select =00 pci clock =01 irq14 =10 gpi/o =11 reserved bit[5] group interrupt enable =1 enable combined irq 2 =0 disable combined irq 2 bit[6] reserved bit[7] output type select 1=open drain 0=push pull gp52 default =0x09 on vbat por 0xca general purpose i/0 bit 5.2 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] reserved bit[4:3] function select =00 drvden1 =01 gpio =10 irq8 =11 nsmi bit[5] group interrupt enable =1 enable combined irq 2 downloaded from: http:///
190 name reg index definition state =0 disable combined irq 2 bit[6] reserved bit[7] output type select 1=open drain 0=push pull gp53 default =0x01 on vbat por 0xcb general purpose i/0 bit 5.3 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] reserved bit[4:3] function select =00 nromcs =01 irq11 =10 gpi/o =11 either edge triggered interrupt 3 bit[5] group interrupt enable =1 enable combined irq 2 =0 disable combined irq 2 bit[6] reserved bit[7] output type select 1=open drain 0=push pull gp54 default = 0x01 on vbat por 0xcc general purpose i/0 bit 5.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] reserved bit[4:3] function select =00 nromoe =01 irq12 =10 gpi/o =11 either edge triggered interrupt 4 bit[5] group interrupt enable =1 enable combined irq 2 =0 disable combined irq 2 bit[6] reserved bit[7] output type select 1=open drain 0=push pull gp60 default = 0x01 on vbat por 0xd0 general purpose i/0 bit 6.0 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] reserved bit[4:3] function select =00 rd0 =01 irq1 =10 gpi/o =11 nsmi downloaded from: http:///
191 name reg index definition state bit[5] group interrupt enable =1 enable combined irq 2 =0 disable combined irq 2 bit[6] reserved bit[7] output type select 1=open drain 0=push pull gp61 default = 0x01 on vbat por 0xd1 general purpose i/0 bit 6.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] reserved bit[4:3] function select =00 rd1 =01 irq3 =10 gpi/o =11 led bit[5] group interrupt enable =1 enable combined irq 2 =0 disable combined irq 2 bit[6] reserved bit[7] output type select 1=open drain 0=push pull gp62 default = 0x01 on vbat por 0xd2 general purpose i/0 bit 6.2 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] reserved bit[4:3] function select =00 rd2 =01 irq4 =10 gpi/o =11 nring bit[5] group interrupt enable =1 enable combined irq 2 =0 disable combined irq 2 bit[6] reserved bit[7] output type select 1=open drain 0=push pull gp63 default = 0x01 on vbat por 0xd3 general purpose i/0 bit 6.3 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] reserved bit[4:3] function select =00 rd3 =01 irq5 downloaded from: http:///
192 name reg index definition state =10 gpi/o =11 wdt bit[5] group interrupt enable =1 enable combined irq 2 =0 disable combined irq 2 bit[6] reserved bit[7] output type select 1=open drain 0=push pull gp64 default = 0x01 on vbat por 0xd4 general purpose i/0 bit 6.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] reserved bit[4:3] function select =00 rd4 =01 irq6 =10 gpi/o =11 p17/p12 1 bit[5] group interrupt enable =1 enable combined irq 2 =0 disable combined irq 2 bit[6] reserved bit[7] output type select 1=open drain 0=push pull note 1: this function is se lected via bit 7 of the ring filter select register. default is p17. gp65 default = 0x01 on vbat por 0xd5 general purpose i/0 bit 6.5 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] reserved bit[4:3] function select =00 rd5 =01 irq7 =10 gpi/o =11 reserved bit[5] group interrupt enable =1 enable combined irq 2 =0 disable combined irq 2 bit[6] reserved bit[7] output type select 1=open drain 0=push pull gp66 default = 0x01 0xd6 general purpose i/0 bit 6.6 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert downloaded from: http:///
193 name reg index definition state on vbat por bit[2] reserved bit[4:3] function select =00 rd6 =01 irq8 =10 gpi/o =11 reserved bit[5] group interrupt enable =1 enable combined irq 2 =0 disable combined irq 2 bit[6] reserved bit[7] output type select 1=open drain 0=push pull gp67 default = 0x01 on vbat por 0xd7 general purpose i/0 bit 6.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 in vert, =0 no invert bit[2] reserved bit[4:3] function select =00 rd7 =01 irq10 =10 gpi/o =11 reserved bit[5] group interrupt enable =1 enable combined irq 2 =0 disable combined irq 2 bit[6] reserved bit[7] output type select 1=open drain 0=push pull gp_int2 default = 0x00 on vbat por 0xef general purpose i/o combined interrupt 2 bits[2:0] reserved, = 000 bit[3] gp irq filter select 0 = debounce filter bypassed 1 = debounce filter enabled bits[7:4] combined irq mapping 1111 = irq15 ......... 0011 = irq3 0010 = invalid 0001 = irq1 0000 = disable gp_int1 default = 0x00 on vbat por 0xf0 general purpose i/o combined interrupt 1 bits[2:0] reserved, = 000 bit[3] gp irq filter select 0 = debounce filter bypassed 1 = debounce filter enabled c downloaded from: http:///
194 name reg index definition state bits[7:4] combined irq mapping 1111 = irq15 ......... 0011 = irq3 0010 = invalid 0001 = irq1 0000 = disable wdt_units default = 0x00 on vcc por or reset_drv 0xf1 watch dog timer units bits[6:0] reserved, = 00000 bit[7] wdt time-out value units select = 0 minutes (default) = 1 seconds note: if the logical device's activate bit is not set then bits 0 and 1 have no effect. c wdt_val default = 0x00 on vcc por or reset_drv 0xf2 watch-dog timer time-out value binary coded, units = minutes(default) or seconds, selectable via bit[7] of reg 0xf1, ld 8. 0x00 time out disabled 0x01 time-out = 1 minute/second ......... 0xff time-out = 255 minutes/seconds c downloaded from: http:///
195 name reg index definition state wdt_cfg default = 0x00 on vtr por bits[0,2-7] are also cleared on v cc por or reset_drv 0xf3 watch-dog timer configuration bit[0] joy-stick enable =1 wdt is reset upon an i/o read or write of the game port =0 wdt is not affected by i/o reads or writes to the game port. bit[1] keyboard enable =1 wdt is reset upon a keyboard interrupt. =0 wdt is not affected by keyboard interrupts. bit[2] mouse enable =1 wdt is reset upon a mouse interrupt =0 wdt is not affected by mouse interrupts. bit[3] pwrled time-out enable =1 enables the power led to toggle at a 1hz rate with 50 percent duty cycle while the watch-dog status bit is set. =0 disables the power led toggle during watch- dog timeout status. bits[7:4] wdt interrupt mapping 1111 = irq15 ......... 0011 = irq3 0010 = invalid 0001 = irq1 0000 = disable c wdt_ctrl default = 0x00 cleared by vtr por 0xf4 watch-dog timer control bit[0] watch-dog status bit, r/w =1 wd timeout occurred =0 wd timer counting bit[1] power led toggle enable, r/w =1 toggle power led at 1hz rate with 50 percent duty cycle. (1/2 sec. on, 1/2 sec. off) =0 disable power led toggle bit[2] force timeout, w =1 forces wd timeout event; this bit is self-clearing bit[3] p20 force timeout enable, r/w = 1 allows rising edge of p20, from the keyboard controller, to force the wd timeout event. a wd timeout event may still be forced by setting the force timeout bit, bit 2. = 0 p20 activity does not generate the wd timeout event. note: the p20 signal will remain high for a minimum of 1us and can remain high indefinitely. therefore, when p20 forced timeouts are enabled, a self-clearing edge-detect circuit is used to generate a signal which is ored with the c downloaded from: http:///
196 name reg index definition state signal generated by the force timeout bit. bit[4] reserved. set to 0. bit[5] stop_cnt: this is used to terminate delay 2 (note 1) without generating a power down. this is used if the software determines that the power down should be aborted. when read, this bit indicates the following: stop_cnt = 0; counter running stop_cnt = 1; counter stopped. note: the write is self clearing. bit[6] restart_cnt: this is used to restart delay 2 (note 1) from the button input to the generation of the power down. when restarted, the count will start over and delay the power down for the time that delay 2 is set for (default=500msec). the software can continue to do this indefinately with out allowing a powerdown. this bit is self clearing. 1=restart; automatically cleared. bit[7] spoff: this is used to force a software power down. this bit is self clearing. note 1: this delay is programmable via the delay 2 time set register at logical device 8, 0xb8. gp1 default = 0x00 on vbat por 0xf6 this register is used to read the value of the gpio pins. bit[0]: gp10 bit[1]: gp11 bit[2]: gp12 bit[3]: gp13 bit[4]: gp14 bit[5]: gp15 bit[6]: gp16 bit[7]: gp17 gp5 default = 0x00 on vbat por 0xf9 this register is used to read the value of the gpio pins. bit[0]: gp50 bit[1]: gp51 bit[2]: gp52 bit[3]: gp53 bit[4]: gp54 bit[7:5]: reserved gp6 default = 0x00 on vbat por 0xfa this register is used to read the value of the gpio pins. bit[0]: gp60 bit[1]: gp61 bit[2]: gp62 bit[3]: gp63 downloaded from: http:///
197 name reg index definition state bit[4]: gp64 bit[5]: gp65 bit[6]: gp66 bit[7]: gp67 note: registers gp1, wdt_ctrl, gp5-6, soft powe r enable and status regist ers are also available at index 01-0f when not in configuration mode. note: gp10-17 can be enabled onto gpint1; gp50-54 and gp60-67 can be enabled onto gpint2. downloaded from: http:///
198 acpi, logical device a table 75 - acpi, logical device a [logical device number = 0x0a] name reg index definition state sleep/wake configuration default = 0x00 on vbat por 0xf0 this register is used to c onfigure the func tionality of the slp_en bit and its associated logic, and the wak_sts bit bit and its associated logic. bit[0] slp_ctrl. slp_ en bit function. 0=default. writing 1 to the slp_en bit causes the system to sequence into the sleeping state associated with the slp_typx fields. 1=writing 1 to the slp_en bit does not cause the system to sequence into the sleeping state associated with the slp_t ypx fields; instead an smi is generated. note: the slp_en_smi bit in the smi status register 2 is set whenever 1 is written to the slp_en bit; it is enabled to generate an smi through bit[0] of this register. bit[1] wak_ctrl. wak_sts bit function 0=default. the wak_sts bit is set on the high-to-low transition of npoweron. 1=the wak_sts bit is set upon any enabled wakeup event and the high-to-low transition of npoweron. bits[2:7] reserved c downloaded from: http:///
199 operational description maximum guaranteed ratings* operating tem perature range.................................................................................................... .0 o c to +70 o c storage temperat ure r ange ..................................................................................................... - 55 o to +150 o c lead temperature range (sol dering, 10 se conds) ...............................................................................+3 25 o c positive voltage on any pin, with respec t to ground ...........................................................................v cc +0.3v negative voltage on any pin, with respec t to ground ............................................................................ ... -0.3v maximum v cc ............................................................................................................................... ................ +7v *stresses above those listed above could cause permanent damage to the device. this is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specif ication is not implied. note: when powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device fa ilure can result. some power supplies exhibit voltage spikes on their outputs when t he ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this po ssibility exists, it is suggested that a clamp circuit be used. dc electrical characteristics (t a = 0 c - 70 c, v cc = +5 v 10%) parameter symbol min typ max units comments i type input buffer low input level high input level v ili v ihi 2.0 0.8 v v ttl levels is type input buffer low input level high input level schmitt trigger hysteresis v ilis v ihis v hys 2.2 250 0.8 v v mv schmitt trigger schmitt trigger iclk input buffer low input level high input level v ilck v ihck 2.2 0.4 v v input leakage (all i and is buffers) low input leakage high input leakage i il i ih -10 -10 +10 +10 a a v in = 0 v in = v cc downloaded from: http:///
200 parameter symbol min typ max units comments oclk2 type buffer low output level high output level output leakage v ol v oh i ol 3.5 -10 0.4 +10 v v a i ol = 2 ma i oh = -2 ma v in = 0 to v cc (note 1) io4 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 4 ma i oh = -2 ma v in = 0 to v cc (note 1) iop4 type buffer low output level high output level output leakage backdrive protected v ol v oh i ol i il 2.4 -10 0.4 +10 10 v v a a i ol = 4 ma i oh = -2 ma v in = 0 to v cc (note 1) v cc =0v; v cc =v tr =0v v in = 6v max o4 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 4 ma i oh = -2 ma v in = 0 to v cc (note 1) o8 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 8 ma i oh = -4 ma v in = 0 to v cc (note 1) downloaded from: http:///
201 parameter symbol min typ max units comments io12 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 12 ma i oh = -6 ma v in = 0 to v cc (note 1) o12 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 12 ma i oh = -6 ma v in = 0 to v cc (note 1) od12 type buffer low output level output leakage v ol i ol -10 0.4 +10 v a i ol = 12 ma v in = 0 to v cc (note 1) op12 type buffer low output level high output level output leakage backdrive protected v ol v oh i ol i il 2.4 -10 0.4 +10 10 v v a a i ol = 12 ma i oh = -6 ma v in = 0 to v cc v cc =0v; v cc =v tr =0v v in = 6v max iop14 type buffer low output level high output level output leakage backdrive protected v ol v oh i ol i il 2.4 -10 0.4 +10 10 v v a a i ol = 14 ma i oh = -14 ma v in = 0 to v cc (note 1) v cc =0v; v cc =v tr =0v v in = 6v max downloaded from: http:///
202 parameter symbol min typ max units comments od14 type buffer low output level output leakage v ol i ol -10 0.4 +10 v a i ol = 14 ma v in = 0 to v cc (note 1) op14 type buffer low output level high output level output leakage backdrive protected v ol v oh i ol i il 2.4 -10 0.4 +10 10 v v a a i ol = 14 ma i oh = -14 ma v in = 0 to v cc v cc =0v; v cc =v tr =0v v in = 6v max iod16 type buffer low output level output leakage v ol i ol -10 0.4 v a i ol = 16 ma v in = 0 to v cc o24 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 24 ma i oh = -12 ma v in = 0 to v cc (note 1) o24pd type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 24 ma i oh = -12 ma v in = 0 to v cc (note 1) od24 type buffer low output level output leakage v ol i ol 0.4 +10 v a i ol = 24 ma v in = 0 to v cc (note 1) chiprotect (slct, pe, busy, nack, nerror, gp10-gp17, gp50- gp54, gp60-gp67,) i il 10 a v cc =0v; v cc =v tr =0v v in = 6v max downloaded from: http:///
203 parameter symbol min typ max units comments backdrive (nstrobe, nautofd, ninit, nslctin, pd0-pd7, gp10- gp17, gp50-gp54, gp60- gp67, nsmi, irq8) i il 10 a v cc =0v; v cc =v tr =0v v in = 6v max v cc supply current active i cci 4.5 30 40 ma all outputs open. trickle supply voltage (note 4) v tr v cc min -.5v v cc max v v cc must not be greater than .5v above v tr v tr supply current active 3 i vri 25 ma all outputs open. battery supply voltage 3 v bat 2.4 3.0 4.0 v v bat supply current 3 standby input leakage 2.0 2.0 3.0 100 a na v cc =v tr =v ss =0v v cc =5v, v bat =3v note 1: output leakage is are measured with the current pins in high impedance. note 2: output leakage is measured with the low driving output off, either for a high level output or a high impedance state. note 3: please contact smsc for the latest values. note 4: the minimum values given for v tr is for v cc active. when v cc =0, the minimum value given for v tr is 0v. capacitance t a = 25 c; fc = 1mhz; v cc = 5v limits parameter symbol min typ max unit test condition clock input capacitance c in 20 pf input capacitance c in 10 pf output capacitance c out 20 pf all pins except pin under test tied to ac ground downloaded from: http:///
204 ac timing capacitive loading for the timing diagrams shown, the following capacitive loads (table 76) are used. table 76 - capacitive loading name capacitance total (pf) sd[0:7] 120 iochrdy 120 irq[3:7,10:12] 60 drq[1:3] 60 nwgate 240 nwdata 240 nhdsel 240 ndir 240 nstep 240 nds[1:0] 240 nmtr[1:0] 240 drvden[1:0] 240 txd1 100 nrts1 100 ndtr1 100 txd2 100 nrts2 100 ndtr2 100 pd[0:7] 240 nslctin 240 ninit 240 nalf 240 nstb 240 kdat 240 kclk 240 mdat 240 mclk 240 downloaded from: http:///
205 iow timing port 92 figure 9 - iow timing for port 92 table 77 - iow timing for port 92 name description min typ max units t1 sax valid to niow asserted 40 ns t2 sdata valid to niow asserted 0 ns t3 niow asserted to sax invalid 10 ns t4 niow deasserted to data invalid 0 ns t5 niow deasserted to niow or nior asserted 100 ns t2 t1 t4 t5 sax sd<7:0> niow t3 downloaded from: http:///
206 power-up timing figure 10 - power-up timing table 78 - power-up timing name description min typ max units t1 vcc slew from 4.5v to 0v 300 s t2 vcc slew from 0v to 4.5v 100 s t3 all host accesses after powerup (note 1) 125 500 s note 1: internal write-protection per iod after vcc passes 4.5 volts on power-up t3 vcc all host accesses t2 t1 downloaded from: http:///
207 button timing figure 11 - button input timing table 79 - button input timing name description min typ max units t r , t f button_in rise/fall time 0.5 s figure 12 - button override timing table 80 - button override timing name description min typ max units t1 button_in hold time for override event 4 s t2 button _in low to npoweron tristate and vcc low and start of blanking period 4 s t3 blanking period after release of button_in 4 s b u tto n _in t f t r vcc npowero n b u tto n _ in t2 t1 t3 blanking period release downloaded from: http:///
208 rom interface figure 13 - rom interface timing note 1: rd[x] driven by fdc 37b72x, sd[x] driven by system note 2 : rd[x] driven by rom, sd[x] driven by fdc37b72x table 81 - rom interface timing name description min typ max units t1 sd[x] valid to rd[x] valid 25 ns t2 nromcs active to rd[x] driven 25 ns t3 nromcs inactive to rd[x] float 25 ns t4 rd[x] valid to sd[x] valid 25 ns t5 nromcs active to sd[x] driven 25 ns t6 nromcs inactive to sd[x] float 25 ns t7 nromoe active to rd[x] float 25 ns t8 nromoe inactive to rd[x] driven 25 ns note 1: outputs have a 50 pf load. t2 t1 t3 t2 t7 t8 t3 t5 t4 t6 note 1 note 2 nromcs nromoe rd[x] sd[x] downloaded from: http:///
209 isa write figure 14 - isa write timing table 82 - isa write timing name description min typ max units t1 sa[x], ncs and aen valid to niow asserted 10 ns t2 niow asserted to niow deasserted 80 ns t3 niow asserted to sa[x], ncs invalid 10 ns t4 sd[x] valid to niow deasserted 45 ns t5 sd[x] hold from niow deasserted 0 ns t6 niow deasserted to niow asserted 25 ns t7 niow deasserted to fintr deasserted (note 1) 55 ns t8 niow deasserted to pinter deasserted (note 2) 260 ns t9 ibf (internal signal) asserted from niow deasserted 40 ns t10 niow deasserted to aen invalid 10 ns note 1: fintr refers to the irq used by the floppy disk note 2: pintr refers to the irq used by the parallel port t10 t3 t1 t2 t4 t6 t5 t8 t9 data a en sa [ x ], niow sd [ x ] fintr pintr ibf t7 downloaded from: http:///
210 isa read figure 15 - isa read timing see timing parameters on next page (table 83). t13 t3 t1 t7 t2 t6 t4 t5 t10 t9 t11 t12 t8 data valid aen sa[x], ncs nior sd[x] pd[x], nerror, pe, slct, ack, busy finter pinter pcobf auxobf1 nior/niow downloaded from: http:///
211 table 83 - isa read timing name description min typ max units t1 sa[x], ncs and aen valid to nior asserted 10 ns t2 nior asserted to nior deasserted 50 ns t3 nior asserted to sa[x], ncs invalid 10 ns t4 nior asserted to data valid 50 ns t5 data hold/float from nior deasserted 10 25 ns t6 nior deasserted 25 ns t8 nior asserted after niow deasserted 80 ns t8 nior/nior, n iow/niow transfers from/to ecp fifo 150 ns t7 parallel port setup to nior asserted 20 ns t9 nior asserted to pinter deasserted 55 ns t10 nior deasserted to finter deasserted 260 ns t11 nior deasserted to pcobf deasserted (notes 3,5) 80 ns t12 nior deasserted to auxobf1 dea sserted (notes 4,5) 80 ns t13 niow deasserted to aen invalid 10 ns note 1: fintr refers to the irq used by the floppy disk. note 2 : pintr refers to the irq used by the parallel port. note 3 : pcobf is used for the keyboard irq. note 4 : auxobf1 is used for the mouse irq. note 5 : applies only if deassertion is performed in hardware. downloaded from: http:///
212 8042 cpu figure 16 - internal 8042 cpu timing table 84 - internal 8042 cpu timing name description min typ max units t1 nwrt deasserted to auxobf1 a sserted (notes 1,2) 40 ns t2 nwrt deasserted to pcobf asserted (notes 1,3) 40 ns t3 nrd deasserted to ibf deasserted (note 1) 40 ns note 1: ibf, nwrt and nrd are internal signals. note 2: pcobf is used for the keyboard irq. note 3: auxobf1 is used for the mouse irq. t2t1 t3 pcobf a uxobf1 nwrt ibf nrd downloaded from: http:///
213 clock timing figure 17 - input clock timing table 85 - input clock timing name description min typ max units t1 clock cycle time for 14.318mhz 70 ns t2 clock high time/low time for 14.318mhz 35 ns t1 clock cycle time for 32khz 31.25 s t2 clock high time/low time for 32khz 16.53 s clock rise time/fall time (not shown) 5 ns figure 18 - reset timing table 86 - reset timing name description min typ max units t4 reset width (note 1) 1.5 s note 1: the reset width is dependent upon the processor clock. the reset must be active while the clock is running and stable. t2 t2 clocki t4 reset_drv downloaded from: http:///
214 single transfer dma figure 19 - single transfer dma timing see timing parameters on next page ( table 87 ). t15 t2 t3 t12 t16 t1 t4 t5 t6 t11 t14 t8 t7 t9 t10 t13 aen fdrq, pdrq ndack nior or niow data (do-d7) tc data valid downloaded from: http:///
215 table 87 - single transfer dma timing name description min typ max units t1 ndack delay time from fdrq high 0 ns t2 drq reset delay from nior or niow 100 ns t3 fdrq reset delay from ndack low 100 ns t4 ndack width 150 ns t5 nior delay from fdrq high 0 ns t6 niow delay from fdrq high 0 ns t7 data access time from nior low 100 ns t8 data set up time to niow high 40 ns t9 data to float delay from nior high 10 60 ns t10 data hold time from niow high 10 ns t11 ndack set up to niow/nior low 5 ns t12 ndack hold after niow/nior high 10 ns t13 tc pulse width 60 ns t14 aen set up to nior/niow 40 ns t15 aen hold from ndack 10 ns t16 tc active to pdrq inactive 100 ns downloaded from: http:///
216 burst transfer dma timing figure 20 - burst t ransfer dma timing see timing parameters on next page ( table 88 ). t15 t2 t3 t12 t16 t1 t4 t5 t6 t11 t14 t8 t7 t9 t10 t13 aen fdrq, pdrq ndack nior or niow data (do-d7) tc data valid data valid downloaded from: http:///
217 table 88 - burst transfer dma timing name description min typ max units t1 ndack delay time from fdrq high 0 ns t2 drq reset delay from nior or niow 100 ns t3 fdrq reset delay from ndack low 100 ns t4 ndack width 150 ns t5 nior delay from fdrq high 0 ns t6 niow delay from fdrq high 0 ns t7 data access time from nior low 100 ns t8 data set up time to niow high 40 ns t9 data to float delay from nior high 10 60 ns t10 data hold time from niow high 10 ns t11 ndack set up to niow/nior low 5 ns t12 ndack hold after niow/nior high 10 ns t13 tc pulse width 60 ns t14 aen set up to nior/niow 40 ns t15 aen hold from ndack 10 ns t16 tc active to pdrq inactive 100 ns downloaded from: http:///
218 disk drive timing figure 21 - disk drive timing (at mode only) table 89 - disk drive timing (at mode only) name description min typ max units t1 ndir set up to step low 4 x* t2 nstep active time low 24 x* t3 ndir hold time after nstep 96 x* t4 nstep cycle time 132 x* t5 nds0-1 hold time from nstep low 20 x* t6 nindex pulse width 2 x* t7 nrdata active time low 40 ns t8 nwdata write data width low .5 y* t9 nds0-1, mtro-1 from end of niow 25 ns *x specifies one mclk period and y specifies one wclk period. mclk = 16 x data rate (at 500 kb/s mclk = 8 mhz) wclk = 2 x data rate (at 500 kb/s wclk = 1 mhz) t3 t1 t2 t4 t5 t6t7 t8 t9 t9 ndir nstep nds0-3 nindex nrdata nwdata niow nds0-1, mtr0-1 downloaded from: http:///
219 serial port figure 22 - serial port timing table 90 - serial port timing name description min typ max units t1 nrtsx, ndtrx delay from niow 200 ns t2 irqx active delay from nc tsx, ndsrx, ndcdx 100 ns t3 irqx inactive delay from nior (leading edge) 120 ns t4 irqx inactive delay from niow (trailing edge) 125 ns t5 irqx inactive delay from niow 10 100 ns t6 irqx active delay from nrix 100 ns t1 t5 t2 t4 t6 t3 niow nrtsx,ndtrx irqx nctsx,ndsrx, ndcdx irqx niow irqx nior nrix downloaded from: http:///
220 parallel port figure 23 - parallel port timing table 91 - parallel port timing name description min typ max units t1 pd0-7, ninit, nstrobe, nautofd delay from niow 100 ns t2 pintr delay from nack, nfault 60 ns t3 pintr active low in ecp and epp modes 200 300 ns t4 pintr delay from nack 105 ns t5 nerror active to pintr active 105 ns t6 pd0 - pd7 delay from iow active 100 ns note: pintr refers to the irq used by the parallel port. t1 t4 t3 t2 t2 t5 t3 niow ninit, nstrobe. nautofd, slctin nack pintr (ecp or epp enabled) nfault (ecp) nerror (ecp) pintr pd0- pd7 t6 npintr (spp) downloaded from: http:///
221 epp 1.9 data or address write cycle figure 24 - epp 1.9 data or address write cycle see timing parameters on next page (table 92). t18 t9 t8 t17 t12 t19 t10 t11 t13 t20 t22 t2 t1 t5 t3 t14 t16 t4 t6 t15 t7 t21 a0-a10 sd<7:0> niow iochrdy nwrite pd<7:0> ndatast naddrstb nwait pdir downloaded from: http:///
222 table 92 - epp 1.9 data or address write cycle timing name description min typ max units t1 niow asserted to pdata valid 0 50 ns t2 nwait asserted to nwrite change (note 1) 60 185 ns t3 nwrite to command asserted 5 35 ns t4 nwait deasserted to command deasserted (note 1) 60 190 ns t5 nwait asserted to pdata invalid (note 1) 0 ns t6 time out 10 12 s t7 command deasserted to nwait asserted 0 ns t8 sdata valid to niow asserted 10 ns t9 niow deasserted to data invalid 0 ns t10 niow asserted to iochrdy asserted 0 24 ns t11 nwait deasserted to iochrdy deasserted (note 1) 60 160 ns t12 iochrdy deasserted to niow deasserted 10 ns t13 niow asserted to nwrite asserted 0 70 ns t14 nwait asserted to command asserted (note 1) 60 210 ns t15 command asserted to nwait deasserted 0 10 s t16 pdata valid to command asserted 10 ns t17 ax valid to niow asserted 40 ns t18 niow asserted to ax invalid 10 ns t19 niow deasserted to niow or nior asserted 40 ns t20 nwait asserted to nwrite asserted (note 1) 60 185 ns t21 nwait asserted to pdir low 0 ns t22 pdir low to nwrite asserted 0 ns note 1: nwait must be filtered to compensate for ri nging on the parallel bus cable. wait is considered to have settled after it does not tr ansition for a minimum of 50 nsec. downloaded from: http:///
223 epp 1.9 data or address read cycle figure 25 - epp 1.9 data or address read cycle see timing parameters on next page (table 93) t20 t19 t11 t22 t13 t12 t8 t10 t18 t23 t24 t27 t9 t21 t17 t2 t25 t5 t4 t16 t1 t14 t26 t28 t3 t7 t15 t6 pdata bus driven by peripheral a0-a10 ior sd<7:0> iochrdy pdir nwrite pd<7:0> datastb addrstb nwait downloaded from: http:///
224 table 93 - epp 1.9 data or address read cycle timing name description min typ max units t1 pdata hi-z to command asserted 0 30 ns t2 nior asserted to pdata hi-z 0 50 ns t3 nwait deasserted to command deasserted (note 1) 60 180 ns t4 command deasserted to pdata hi-z 0 ns t5 command asserted to pdata valid 0 ns t6 pdata hi-z to nwait deasserted 0 s t7 pdata valid to nwait deasserted 0 ns t8 nior asserted to iochrdy asserted 0 24 ns t9 nwrite deasserted to nior asserted (note 2) 0 ns t10 nwait deasserted to iochrdy deasserted (note 1) 60 160 ns t11 iochrdy deasserted to nior deasserted 0 ns t12 nior deasserted to sdata hi-z (hold time) 0 40 ns t13 pdata valid to sdata valid 0 75 ns t14 nwait asserted to command asserted 0 195 ns t15 time out 10 12 s t16 nwait deasserted to pdat a driven (note 1) 60 190 ns t17 nwait deasserted to nwrite modified (notes 1,2) 60 190 ns t18 sdata valid to iochrdy deasserted (note 3) 0 85 ns t19 ax valid to nior asserted 40 ns t20 nior deasserted to ax invalid 10 10 ns t21 nwait asserted to nwrite deasserted 0 185 ns t22 nior deasserted to niow or nior asserted 40 ns t23 nwait asserted to pdir set (note 1) 60 185 ns t24 pdata hi-z to pdir set 0 ns t25 nwait asserted to pdata hi-z (note 1) 60 180 ns t26 pdir set to command 0 20 ns t27 nwait deasserted to pdir low (note 1) 60 180 ns t28 nwrite deasserted to command 1 ns note 1: nwait is considered to have settled after it does not transition for a minimum of 50 ns. note 2: when not executing a write cy cle, epp nwrite is inactive high. note 3: 85 is true only if t7 = 0. downloaded from: http:///
225 epp 1.7 data or address write cycle figure 26 - epp 1.7 data or address write cycle see timing parameters on next page (table 94). t18 t9 t8 t17 t6 t12 t19 t10 t20 t11 t13 t2 t1 t5 t3 t16 t4 t21 a 0-a10 sd<7:0> niow iochrdy nwrite pd<7:0> ndatast naddrstb nwait pdir downloaded from: http:///
226 table 94 - epp 1.7 data or address write cycle timing name description min typ max units t1 niow asserted to pdata valid 0 50 ns t2 command deasserted to nwrite change 0 40 ns t3 nwrite to command 5 35 ns t4 niow deasserted to command deasserted (note 2) 50 ns t5 command deasserted to pdata invalid 50 ns t6 time out 10 12 s t8 sdata valid to niow asserted 10 ns t9 niow deasserted to data invalid 0 ns t10 niow asserted to iochrdy asserted 0 24 ns t11 nwait deasserted to io chrdy deasserted 40 ns t12 iochrdy deasserted to niow deasserted 10 ns t13 niow asserted to nwrite asserted 0 50 ns t16 pdata valid to command asserted 10 35 ns t17 ax valid to niow asserted 40 ns t18 niow deasserted to ax invalid 10 s t19 niow deasserted to niow or nior asserted 100 ns t20 nwait asserted to io chrdy deasserted 45 ns t21 command deasserted to nwait deasserted 0 ns note 1: nwrite is controlled by clearing the pdir bi t to "0" in the control register before performing an epp write. note 2: the number is only valid if nwait is active when iow goes active. downloaded from: http:///
227 epp 1.7 data or address read cycle figure 27 - epp 1.7 data or address read cycle see timing parameters on next page (table 95). t20 t19 t11 t15 t22 t13 t12 t3 t8 t10 t5 t4 t23 t2 t21 a0-a10 nior sd<7:0> iochrdy nwrite pd<7:0> ndatastb naddrstb nwait pdir downloaded from: http:///
228 table 95 - epp 1.7 dat or address read cycle timing name description min typ max units t2 nior deasserted to co mmand deasserted 50 ns t3 nwait asserted to iochrdy deasserted 0 40 ns t4 command deasserted to pdata hi-z 0 ns t5 command asserted to pdata valid 0 ns t8 nior asserted to iochrdy asserted 24 ns t10 nwait deasserted to io chrdy deasserted 50 ns t11 iochrdy deasserted to nior deasserted 0 ns t12 nior deasserted to sdata high-z (hold time) 0 40 ns t13 pdata valid to sdata valid 40 ns t15 time out 10 12 s t19 ax valid to nior asserted 40 ns t20 nior deasserted to ax invalid 10 ns t21 command deasserted to nwait deasserted 0 ns t22 nior deasserted to niow or nior asserted 40 ns t23 nior asserted to command asserted 55 ns note: write is controlled by setting the pdir bit to "1" in the control register before performing an epp read. downloaded from: http:///
229 ecp parallel port timing parallel port fifo (mode 101) the standard parallel port is run at or near the peak 500kbytes/sec allowed in the forward direc- tion using dma. the st ate machine does not examine nack and begins the next transfer based on busy. refer to figure 29. ecp parallel port timing the timing is designed to allow operation at approximately 2.0 mbytes/sec over a 15ft cable. if a shorter cable is used then the bandwidth will increase. forward-idle when the host has no data to send it keeps hostclk (nstrobe) high and the peripheral will leave periphclk (busy) low. forward data transfer phase the interface transfers data and commands from the host to the peripheral using an interlocked periphack and hostclk. the peripheral may indicate its desire to send data to the host by asserting nperiphrequest. the forward data transfer phase may be entered from the forward-idle phas e. while in the forward phase the peripheral may asynchronously assert the nperiphrequest (nfault) to request that the channel be reversed. when the peripheral is not busy it sets periphack (busy) low. the host then sets hostclk (nstrobe) lo w when it is prepared to send data. the data must be stable for the specified setup time prior to the falling edge of hostclk. the peripheral then sets periphack (busy) high to acknowledge the handshake. the host then sets hostclk (nstrobe) high. the peripheral then accept s the data and sets periphack (busy) low, completing the transfer. this sequence is shown in figure 29. the timing is designed to provide 3 cable round-trip times for data setup if data is driven simultaneously with hostclk (nstrobe). reverse-idle phase the peripheral has no data to send and keeps periphclk high. the host is idle and keeps hostack low. reverse data transfer phase the interface transfers data and commands from the peripheral to the host using an interlocked hostack and periphclk. the reverse data transfer phase may be entered from the reverse- idle phase. after the previous byte has beed accepted the host sets hostack (nalf) low. the peripheral then sets periphclk (nack) low when it has data to send. the dat a must be stable for the specified setup time prior to the falling edge of periphclk. when the host is ready to accept a byte it sets hostack (nalf) high to acknowledge the handshake. the peripheral then sets periphclk (nack) high. after the host has accepted the data it sets hostack (nalf) low, completing the trans- fer. this sequence is shown in figure 30. output drivers to facilitate higher performance data transfer, the use of balanced cmos active drivers for critical signals (data, hostack, hostclk, periphack, periphclk) are used ecp mode. because the use of active drivers can present compatibility problems in compatible mode (the control signals, by tradition, are specified as open-collector), the drivers are dynamically changed from open-collector to totem-pole. the timing for the dynamic driver change is specified in the ieee 1284 extended capabilities port protocol and isa interface standard , rev. 1.14, july 14, 1993, available from microsoft. the dynamic driver change must be implemented properly to prevent glitching the outputs. downloaded from: http:///
230 table 96 - parallel port fifo timing name description min typ max units t1 data valid to nstrobe active 600 ns t2 nstrobe active pulse width 600 ns t3 data hold from nstrobe inactive (note 1) 450 ns t4 nstrobe active to busy active 500 ns t5 busy inactive to nstrobe active 680 ns t6 busy inactive to pdata invalid (note 1) 80 ns note 1: the data is held until busy goes inactive or for time t3, whichever is longer. this only applies if another data transfer is pending. if no other data trans fer is pending, the data is held indefinitely. t3 t6 t1 t2 t5 t4 pdata nstrobe busy figure 28 - parallel port fifo timing downloaded from: http:///
231 figure 29 - ecp parallel port forward timing table 97 - ecp parallel port forward timing name description min typ max units t1 nautofd valid to nstrobe asserted 0 60 ns t2 pdata valid to nstrobe asserted 0 60 ns t3 busy deasserted to nautofd changed (notes 1,2) 80 180 ns t4 busy deasserted to pdata changed (notes 1,2) 80 180 ns t5 nstrobe deasserted to busy asserted 0 ns t6 nstrobe deasserted to busy deasserted 0 ns t7 busy deasserted to nstrobe asserted (notes 1,2) 80 200 ns t8 busy asserted to nstrobe deasserted (note 2) 80 180 ns note 1: maximum value only applies if there is data in the fifo waiting to be written out. note 2: busy is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. t3t4 t1 t2 t7 t8 t6 t5 t6 nautofd pdata<7:0> busy nstrobe downloaded from: http:///
232 figure 30 - ecp parallel port reverse timing table 98 - ecp parallel port reverse timing name description min typ max units t1 pdata valid to nack asserted 0 ns t2 nautofd deasserted to pdata changed 0 ns t3 nack asserted to nautofd deasserted (notes 1,2) 80 200 ns t4 nack deasserted to nautofd asserted (note 2) 80 200 ns t5 nautofd asserted to nack asserted 0 ns t6 nautofd deasserted to nack deasserted 0 ns note 1: maximum value only applies if there is room in the fifo and terminal count has not been received. ecp can stall by keeping nautofd low. note 2: nack is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. t2 t1 t5 t6 t4 t3 t4 pdata<7:0> nack nautofd downloaded from: http:///
233 serial port infrared timing irda sir receive figure 31 - irda si r receive timing t1 t2 t2 t1 0 101 0 0 11011 data irrx n irrx t1t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 paramete r min t yp max units 1.41.4 1.4 1.4 1.4 1.4 1.4 2.713.69 5.53 11.0722.13 44.27 88.55 s s s s s s s s s s s s s s pulse width a t pulse width a t pulse width a t pulse width a t pulse width a t pulse width a t pulse width a t bit time at bit time at bit time at bit time at bit time at bit time at bit time at 1.6 3.22 4.89.7 19.5 3978 8.6817.4 2652 104208 416 1. receive pulse detection criteria: a received p ulse is considered received pulse is a minimum of 1 41s 2. irrx: l5 , crf1 bit 0 nirrx: l5 , crf1 bit 0 = 0 downloaded from: http:///
234 irda sir transmit figure 32 - irda si r transmit timing t1t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 parameter mi n 1.41 1.41 1.41 1.41 1.41 1.41 1.41 ma x 2.71 3.69 5.53 11.07 22.13 44.27 88.55 units s s s s s s s s s s s s s s pulse width at 115kbaud pulse widt h at 57. 6kbaud pulse widt h at 38. 4kbaud pulse widt h at 19. 2kbaud pulse widt h at 9. 6kbaud pulse widt h at 4. 8kbaud pulse widt h at 2. 4kbaud bit t ime at 115kbaud b it tim e at 57. 6kbaud b it tim e at 38. 4kbaud b it tim e at 19. 2kbaud bit tim e at 9.6kbaud bit tim e at 4.8kbaud bit tim e at 2.4kbaud typ 1.6 3.22 4.8 9.7 19.5 3978 8.68 17.4 2652 104208 416 t1 t2 t2 t1 0 10 1 0 0 11 0 11 dat a irtx n i rt x notes: 1. irda @ 115k i s hpsir com pati ble. irda @ 2400 wi ll al low compatibilit y with hp95lx and 48sx. 2. irt x: l5, crf 1 bit 1 = 1 (default) nirtx: l5, crf1 bit 1 = 0 downloaded from: http:///
235 ask ir receive figure 33 - amplitude shift keyed ir receive timing t1t2 t3 t4 t5 t6 pa rameter min typ max units 0.8 0.8 0.8 0.8 1.2 1.2 1.2 1.2 s s s s s s m odu lated out put b it t ime off bit t ime m odu l ated outp ut " on" m odu l ated out put " off" m odu l ated outp ut " on" m odu l ated out put " off" 11 1 1 note s: 1 . irrx: l 5, crf 1 bit 0 = 1 n irrx: l5 , crf 1 bit 0 = 0 (de fault) m irrx, nmi rrx are the mod ulate d ou t p uts t1 t2 t3 t4 t5 t6 01010011011 dat a irrx n irrx mirrx nm irrx downloaded from: http:///
236 ask ir transmit figure 34 - ask ir transmit timing t1t2 t3 t4 t5 t6 parameter min typ max units 0.8 0.8 0.8 0.8 1.2 1.2 1.2 1.2 s s s s s s modulated output bit time off bit time modulated output "on" modulated output "off" modulated output "on" modulated output "off" 11 1 1 notes: 1. irtx: l5, crf1 bit 1 = 1 (default) nirtx: l5, crf1 bit 1 = 0 mirtx, nmirtx are the modulated outputs t1 t2 t3 t4 t5 t6 01010 011011 data irtx n irtx mirtx nmirtx downloaded from: http:///
237 figure 35 C 128 pin qfp package outline 3) package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25 mm. notes: 1) coplanarity is 0.08 mm or 3.2 mils maximum. 2) tolerance on the position of the leads is 0.080 mm maximum. 4) dimensions for foot length l measured at the gauge plane 0.25 mm above the seating plane. 5) details of pin 1 identifier are optional but must be located within the zone indicated. 6) controlling dimension: millimeter l1 l detail "a" r1 r2 4 0 0.10 -c- h a a1 a2 1 see detail "a" 0 aa1 a2 d d1 e e1 h min 0.05 2.55 23.65 19.9 17.65 13.9 nom 23.9 20 17.9 14 max 3.4 0.5 3.05 24.15 20.1 18.15 14.1 nom 0.8 1.95 ll1 e 0 w r1 r2 min 0.65 0 0.1 0.13 0.13 max 0.95 7 0.3 0.3 0.5bsc e1 e d1 d w 3 3 e 2 d1/4 e1/4 5 39 38 64 65 102 103 128 1 downloaded from: http:///
238 fdc37b72x erratta sheet page section/figure/entry correction date revised 85 figure 3/heading see italicized text 1/8/99 142 table see italicized text 1/8/99 downloaded from: http:///
80 arkay drive, hauppauge, ny 11788 (631) 435-6000, fax (631) 273-3123 copyright ? 2007 smsc or its subs idiaries. all rights reserved. circuit diagrams and other information rela ting to smsc products are included as a m eans of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. sm sc reserves the right to make changes to specifications and pr oduct descriptions at any time without notice. contact your local smsc sales office to obtain the latest specifications before placing your product order. the pr ovision of this information does not convey to the purchaser of the des cribed semiconductor devices any licenses under any patent rights or ot her intellectual property rights of smsc or others. all sales a re expressly conditional on your agreement to the terms and conditions of the most recently dated ve rsion of smsc's standard terms of sale agreement dated before the dat e of your order (the "terms of sale agreem ent"). the product may contain design defects or errors known as anomalies which may cause the product's f unctions to deviate from published s pecifications. a nomaly sheets are available upon request. smsc products are not designed, intended, aut horized or warranted for use in any life support or other application where product failure c ould cause or contribute to per sonal injury or severe property damage. any and all such uses without prior written approval of an office r of smsc and further testing and/or modifi cation will be fully at the risk of the c ustomer. copies of this document or ot her smsc literature, as well as the terms of sale agreement, may be obtained by visiting smscs website at http://www.smsc.com. smsc is a registered tr ademark of standard microsystems corporation (smsc). product names and company names are the trademarks of their respective holders. smsc disclaims and excludes any and all warranties, including without limitation any and all implied warranties of merchantability, fitness for a particular purpose, title, and against infringement and the like, and any and all warranties arising from any course of dealing or usage of trade. in no event shall smsc be liable for an y direct, incident al, indirect, specia l, punitive, or consequential damages; or for lost data, profit s, savings or revenues of any kind; regardless of the form of action, whether based on contract; tort; negligence of smsc or others; strict liability; breach of warranty; or otherwise; whet her or not any remedy of buyer is held to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages. fdc37b72x rev. 02-16-07 downloaded from: http:///

▲Up To Search▲

Price & Availability of FDC37B727-NS

	To Download FDC37B727-NS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .